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WD2511/WD2840 
Technical Package 
April, 1984 



WESTERN DIGITAL 

CORPORA T I O N 



~a 



WD2511/WD2840 

Technical Package 

April, 1984 



TABLE OF CONTENTS 

WD2511 X.25 Packet Network Interface (LAPB) 1 

Application Note Using The WD2511 33 

WD2840 Local Network Token Access Controller 53 

WD2840 Application Note 89 



WESTERN DIGITAL 

CORPORA r I O N 




WESTERN DIGITAL 

CORPORATION 

WD2511 X.25 Packet Network Interface (LAPB) 



FEATURES 

• Packet switching controller, complies with CCITT 
Recommendation X.25, level 2, LAPB. 

• Programmable primary timer (T1) and retransmis- 
sion counter (N2). 

• Programmable A-field which provides a wider range 
of applications than defined by X.25. These include: 
DTE-to-DTE connection, multipoint and loop-back 
testing. 

• Direct memory access (DMA) transfer: two chan- 
nels; one for transmit and one for receive. Send/ 
receive data accessed by indirect addressing 
method. Sixteen output address lines. 

• Zero bit insertion and deletion. 

• Automatic appending and testing of FCS field. 

• Computer bus interface structure: 8 bit bi-directional 
data bus. CS, WE, RE and four input address lines. 

• DC to 1.1 MBPS data rate. 

• TTL compatible. 

• 48 pin dual in-line packages. 



NO 
CONNECTION I 


1 ^ 48 

2 47 


zd v CC (+sv) 


REPLY rzz 


ZD IA1 


WE nz 


3 


46 


ZD iao 


CS CZ 


4 


45 ZD IA2 


RE CZ 


5 


44 


ZD IA3 


CLK I 


6 


43 


ZH INTR 


MR I 


7 


42 


ZD V DD ( + 12V) 


DALO LZI 


8 


41 


ZD A5 


DAL1 LZI 


9 


40 


ZH A4 


DAL2 LZI 


10 


39 


ZD A3 


DAL3 CZ 


11 


38 


ZD A2 


DAL4 LZI 


12 


37 


ZD A15 


DAL5 CZ 


13 


36 


ZD A14 


DAL6 LZI 


14 


35 


ZD A13 


DAL7 LZI 


15 


34 


ZD A12 


RD CZ 


16 


33 


ZD An 


RC LZI 


17 


32 


ZD aio 


(GND)V SS LZI 


18 


31 


Z3 A9 


TCLZI 


19 


30 


ZD A8 


TD LZI 


20 


29 


ZDA7 


RTS LZI 


21 


28 ZD A6 


CTS I 


22 


27 ZD A0 


DRQQ I 


23 


26 


ZDai 


DRQI LZI 


24 


25 


ZD dack 



3 

a 

Ol 



PIN DESIGNATION 



DESCRIPTION 

The WD2511 is a MOS/LSI device which handles bit- 
oriented, full-duplex serial data communications with 
DMA, which conforms to CCITT X.25's LAPB with pro- 
grammable enhancements. 

The device is fabricated in N-Channel silicon gate MOS 
technology and is TTL compatible on all inputs and 
outputs. 



APPLICATIONS 

X.25 PACKET SWITCHING CONTROLLER 

PART OF DTE OR DCE 

PRIVATE PACKET NETWORKS 

LINK LEVEL CONTROLLER 

STORE AND FORWARD SYSTEM 

HIGH REL POINT TO POINT COMMUNICATIONS 

BIT ORIENTED PROTOCALS WITH BUILT IN DMA 



INTERFACE SIGNALS DESCRIPTION (All signals are TTL compatible.) 


PIN 
NUMBER 


SYMBOL 


PIN NAME 


FUNCTION 


1 
2 




No Connection 
Reply 


Leave pin open. 

An active low output indicates the WD2511 has 
either a CS»RE or a CS«WE input condition. 


REPLY 


3 


WE 


Write Enable 


The data on the DAL are written into the 
selected register when CS and WE are low. 


4 


CS 


Chip Select 


Active low chip select for CPU control of I/O 
registers. 


5 


RE 


Read Enable 


The contents of the selected register is placed 
on DAL when CS and RE are low. 


6 


CLK 


Clock 


Clock input used for internal timing. Must be 
square wave and should be greater than 500 
KHz. 


7 


MR 


Master Reset 


Active low initializes the chip. All registers reset 
to zero, except control bits MDISC and LINK 
which ar§_set to 1 . DACK must be stable high 
before MR goes high. 


8-15 


DAL0-DAL7 


Data Access Lines 


An 8-bit bi-directional three-state data bus for 
CPU and DMA controlled transfers. 


16 


RD 


Receive Data 


Receive serial data input. 


17 


RC 


Receive Clock 


This is a 1 x clock input. RD is sampled on the 
rising edge of RC. 


18 


vss 


Ground 


Ground. 


19 


TC 


Transmit Clock 


A 1x clock input. TD changes on the falling 
edge of TC. 


20 


TD 


Transmit Data 


Transmit serial data output. 


21 


RTS 


Request-To-Send 


An open collector (drain) output which goes 
low when the WD2511 is ready to transmit 
either flags or data. 


22 
23 


CTS 


Clear-To-Send 
DMA Request Out 


An active low input which signals the WD2511 
that transmission may begin. If high, the TD 
output is forced high. May be hard-wired to 
ground. 

An active low output signal which initiates CPU 
bus request so the WD2511 can output data 
onto the bus. 


DRQO 


24 
25 


DRQI 


DMA Request In 
DMA Acknowledge 


An active low output signal which intitiates 
CPU bus request so that data may be input to 
the WD2511 . 

An active low input from the CPU in response 
to DRQI or DRQO. DACK must not be low if CS 
and RE are low or if CS and WE are low. 


DACK 


27, 26, 
38-41, 
28-37 


A0-A15 


Address Lines Out 


Sixteen address outputs from the WD2511 for 
DMA operation. If the control bit ADRV is 1, the 
outputs are TTL drives at all times. If ADRV is 0, 
the outputs are three-state, and are Hl-Z when- 
ever DACK is high. (ADRV is in Control Regis- 
ter #1 .) 


42 


vdd 


Power Supply 


+ 12VDC power supply input. 



INTERFACE SIGNALS DESCRIPTION CONTINUED (All signals are TTL compatible.) 



PIN 
NUMBER 


SYMBOL 


PIN NAME 


FUNCTION 


43 


INTR 


Interrupt Request 


An active low interrupt service request output. 
Returns to high when Status Register #1 is 
read. 


46, 47, 
45,44 


IA0-IA3 


Address Lines In 


Four address inputs for CPU controlled read/ 
write operation of the I/O registers in the 
WD2511. If ADRV = 0, these may be tied to A0- 
A3. (ADRV is in Control Register = 1 .) 


48 


vcc 


Power Supply 


+ 5VDC power supply input. 



o 

io 



ORGANIZATION 

Note: See appendix D for a glossary of terms used 
throughout this document. 

A detailed block diagram of the WD2511 is shown in 
Figure 1 . 

Mode control and monitor of status by the user's CPU is 
performed through the Read/Write Control circuit 
which reads from or writes into I/O registers addressed 
by IA0-IA3. 

Transmit and receive data are accessed through the 
DMA control. Serial data is generated and received by 
the bit-oriented controllers. 

Internal Control of the WD2511 is by means of three 
internal microcontrollers; one for transmit, one for 



receive, and one for overall control. 

Parallel transmit data are entered into the Transmitter 
Holding Register (THR), and then presented to the 
Transmitter Register (TR) which converts the data to a 
serial bit stream. The Cyclic Redundancy Check (CRC) 
is computed in the 16-bit CRC register, and the result 
becomes the transmitted Frame Check Sequence 
(FCS). 

Parallel receive data enters the Receiver Holding Reg- 
ister (RHR) from the 24-bit serial Receiver Register 
(RR). The 24-bit length of RR permits stripping of the 
FCS prior to transfer in to the RHR. The receiver CRC 
register is used to test the validity of the received FCS. 
A 3-stack FIFO is included in the receiver. 



cs- 

RE- 

WE- 

IA0-IA3- 

REPLY - 



READ- 
WRITE 
CONTROL 
LOGIC 



I/O 

REGISTERS 
16x8 



Tl 
COUNTER 



+ 12V- 
+ 5V- 
MR - 
CLK - 
GND- 



N2 
COUNTER 



INTERNAL 

REGISTERS 

16X8 



MICRO 
C 
O 

N 
T 
R 
O 

L 
L 
E 
R 



DMA 
A 
D 
D 
R 
E 
S 
S 
E 
S 



DMA 

CONTROL 

LOGIC 



•DRQO 

- DROT 

DACK 



RECEIVER 
MICRO-CONTROLLER 



TRANSMITTER 
MICRO-CONTROLLER 



RHR 8 



*FCS 
I ER ROR 



FIFOg 



|— »*ABORT [*" 
(♦SHORT L_ 



CRC 



ZERO 
DELETE 



THR 8 



} 3-STACK 



f CRC ""I FLAG-.H 
1 ' ABORT— *- 

TR 8 1 1 ▼» [ ZERO I^L 
B INSERT 



LOOP TEST 



TC 
CTS 
■RTS 



■*-TD 



Figure 1 WD2511 BLOCK DIAGRAM — DETAILED 



FRAME FORMAT 

^ The WD2511 performs "bit-oriented" data communica- 

*^ tions control. According to the general format for bit-ori- 

g ented procedures (HDLC, SDLC, ADCCP), each serial 

<ji block of data is called a frame. 

-j. Each frame starts and ends with a Flag (01111110). A 
single flag may be used both as the closing flag of one 
frame and the opening flag of the next frame. In 
between flags, data transparency is provided by the 
insertion of a bit after all sequences of 5 contiguous 1 
bits. The receiver will strip the inserted bits. The last 
16-bits before the closing flag is in the Frame Check 
Sequence (FCS). Each frame also includes address 
and control fields (A and C fields). 

The FCS calculation includes all data between the 
opening flag and the first bit of the FCS, except for 0's 
inserted for transparency. The 16-bit FCS has the fol- 
lowing characteristics: 

Polynomial = X16 + X12 + x5 + 1 

Transmitted Polarity— Inverted 

Transmitted Order —High Order Bit First 

Preset Value — All I's 



After the frame is received, if there were no errors then 
the remainder in the CRC register (internal in the 
WD2511)willbe: 

1111000010111000 FOB8 

The WD2511 generates and tests the Flag, FCS, A- 
Field, C-Field, and performs zero bit insertion and 
deletion. 

According to the X.25 protocol, there are three types of 
frames: supervisory (S-frame), un-numbered (U- 
frame), and information (l-frame). The WD2511 per- 
forms frame level (level 2) link access control. All S- and 
U-frames are automatically generated and tested by 
the WD2511 . The user need only be concerned with the 
l-frames, which are packets. 

The WD2511 will transmit contiguous flags for 
interframe time fill (full duplex mode). 



-I-FRAME(PACKET)- 



-l-FIELD (PACKET DATA)- 



FLAG 


ADDRESS 


CONTROL 


PACKET 

CONTROL 

INFORMATION 


USER DATA 


FCS 


FLAG 



-X.25 LEVEL 2- 



APPENDED »> 

BY 
WD2511 



X.25 LEVEL 3 



APPLICATION 
— SOFTWARE - 



-DMAACCESSED- 



-X.25LEVEL2- 



-4 APPENDED 

BY 
WD251 1 



X.25 MODE 



NOTE: X.25 Level 1, is the Physical Interface 



CPU INTERFACE 



n 



MEMORY 



<r u <r v 



v v 



MODEM 
CONTROLS 



CTS 



LEVEL 1 
INTERFACE 



MODEM 



+ 12VDC +5VDC GND 

Figure 2. SYSTEM CONNECTION 



O 
Ol 



II. PROGRAMMING THROUGH REGISTERS 

The WD2511 is controlled and monitored by sixteen I/O 
registers. 



Control, status, and error bits will be referred to as CR, 
SR, or ER, respectively, along with two digits. For 
example, SR16 refers to status register #1 and bit 6, 
which is "XBA" 



REGISTER DEFINITION 



REG 

# 


IA3 


IA2 


IA1 


IA0 


REGISTER 


REGISTER 
GROUPING 



1 
2 
3 
4 
5 















1 
1 





1 
1 







1 



1 



1 


CRO 
CR1 
*SR0 
*SR1 
*SR2 
*ER0 


OVERALL CONTROL 

AND 

MONITOR 


6 

7 






1 
1 


1 
1 




1 


'CHAIN MONITOR 
*RECEIVEDC-FIELD 


RECEIVER 
MONITOR 


8 
9 














1 


T1 
N2/T1 


TIMER 


A 
B 
C 
D 







1 
1 


1 
1 







1 



1 


TLOOK HI 
TLOOK LO 

CHAIN/BUFFER SIZE 
NOT USED 


DMA SET-UP 


E 
F 




1 
1 


1 
1 




1 


XMT COMMAND "E" 

XMT RESPONSE "F" (Note 1) 


"A" FIELD 



*CPU READ ONLY. (Write Not Possible) 

NOTE: 

1 . Registers E and F should be set-up while MDISC = 1 . 



o 

Ol 



CONTROL, STATUS, ERROR REGISTERS 


REGISTER 


7 


6 


5 


BIT# 
4 


3 


2 


1 





CRO 







H/F 


ACTIVE/ 
PASSIVE 


LOOP 
TEST 


RAMT 


RECR 


MDISC 


ADISC 


CR1 


TXMT 


TRCV 


xi 


ADRV 











SEND 


SRO 


NA2 


NA1 


NAO 


RNRR 


NB2 


NB1 


NBO 


RNRX 


SR1 


1PKR 


1XBA 


1 ERROR 





NE2 


NE1 


NEO 





SR2 


T10UT 


IRTS 


REC 
IDLE 
















LINK 


ERO 


ER07 


ER06 


ER05 


ER04 


ER03 


ER02 


ER01 


EROO 



1 Causes Interrupt (INTR Goes Low). 



REGISTER 



CR07 



CR06 



CR05 



CONTROL REGISTER 
CR04 CR03 



CR02 



CR01 



CROO 



CRO 



ADISC 



H/F 



ACTIVE/ 
PASSIVE 



LOOP 
TEST 



RAMT 



RECR 



MDISC 



BIT 



DESCRIPTION 



CROO 



CR01 

CR02 
CR03 

CR04 

CR05 
CR06 
CR07 



MDISC (mandatory disconnect command) MDISC will cause a logical disconnect in the 
link. No DMA accessed data will be transferred as long as MDISC = 1 . After Master 
Reset, MDISC will be set. The WD2511 will neither transmit nor accept received data 
until MDISC = 0. 

RECR (Receiver Ready) indicates the CPU's is receiver buffer is Ready (CR01 = 1). If 
RECR = 1, the WD2511 may begin receiving l-frames. (See SROO) 

RAMT — Internal Register Test when set. (See Self Tests) 

The LOOP TEST bit will connect the transmit data output to the receive data input. The 
receiver input pins RD and RC are then logically disconnected from the internal circuitry. 
The "E" and "F" data registers of the A-field must be equal. 

The Active/Passive bit when set, in conjunction with MDISC = 0, will cause the WD2511 
to initiate link set-up. When this bit is reset, the WD2511 will wait for a link setup from the 
remote station. 

H/F selects full duplex if CR05 = 0, and half duplex if CR05 = 1 . (See Appendix A). 

Unused control bits should remain at 0. 



ADISC (disconnect) is used when CR04 = 1 (ACTIVE). When the WD2511 actively initi- 
ates link set-up, a DISC will be transmitted and acknowledged prior to transmission of 
the SABM if CR07 = 0. If CR07 = 1, the WD2511 will send only the SABM. 



CONTROL REGISTER 1 



REGISTER 


CR17 




CR16 


CR15 


CR14 


CR13 


CR12 


CR11 


CR10 


CR1 


TXMT 


TRCV 


XI 


ADRV 











SEND 


BIT 


DESCRIPTION 


CR10 

CR11-13 
CR14 

CR15 

CR16 
CR17 


The SEND bit is used to command the WD2511 to send the next packet or packets. If 
SEND = 1, the WD2511 will read from TLOOK the BRDY bit of the next segment for 
transmission. If BRDY = 0, the WD2511 will clear SEND and no action occurs. If BRDY 
= 1, the WD2511 will then read TSADR and TCNT, followed by the transmission of that 
buffer. After transmission, the WD2511 clears BRDY of the segment just transmitted, and 
reads BRDY of the next segment. If 1, the next segment is transmitted. If 0, the SEND bit 
is cleared, and transmission of packets is stopped. As a matter of good practice, the CPU 
should set SEND each time a BRDY bit is set. 

Unused bits, write in O's. 

The ADRV (ADDRESS VALID) bit is the control for the 16 bit output addresses (A0-A15). 
If ADRV = 0, the outputs are tri-state and are in Hl-Z, except when DACK is low. If ADRV 
= 1, the outputs are always low impedance (TTL), and are forced high-level (logical 1) 
when DRQO, DRQI and DACK are all high. 

XI -^[Transparent l-field) Used when TXMT = 1 

XI = O.Frame> 3 bytes excluding FCS and Flag. 
XI = 1. Frame < 3 bytes excluding FCS and Flag. 

TRCV — Transparent Receive. Receive all frames including unknown frames. See 
Appendix A. 

TXMT — Transparent transmit. See Appendix A. 



a 

01 



STATUS REGISTER 



REGISTER 


SR07 




SR06 


SR05 


SR04 


SR03 


SR02 


SR01 


SROO 


SRO 


NA2 


NA1 


NAO 


RNRR 


NB2 


NB1 


NBO 


RNRX 


BIT 


DESCRIPTION 


SROO 

SR03-SR01 
SR04 

SR07-SR05 


RNRX. An RNR has been transmitted or will be at next opportunity. The CPU should set 
RECR when receive buffers are available. 

NB2-NB0. Next block to be transmitted. 

RNRR. This bit is set when an RNR frame is received. Once set, it is cleared when an 
RR, REJ, SABM, or UA is received. 

NA2-NA0. Next block of transmitted data to be Acknowledged. 



STATUS REGISTER 1 



IO 



REGISTER 


SR17 




SR16 


SR15 


SR14 


SR13 


SR12 


SR11 


SR10 


SR1 


-|PKR 


-|XBA 


1 ERROR 





NE2 


NE1 


NEO 





BIT 


DESCRIPTION 


SR10 

SR13-SR11 
SR14 
SR151 

SRI61 
SR171 


(not used) 

NE2-NE0. Next Expected packet number and next RLOOK segment number. 

(not used) 

The ERROR bit indicates: 1) An error has occurred which is not recoverable by the 
WD2511 or 2) A significant event has occured. 

For the specific reason for the ERROR bit being set, see error register (ERO) on next 
page. 

The XBA (transmitted block acknowledgement) bit set, indicates that a previously trans- 
mitted Block, or Blocks, have been acknowledged by the remote device. Upon acknowl- 
edgement, the ACK'ED bit is set to "1" for each segment in TLOOK which was 
acknowledged. 

The PKR bit stands for Packet Received. PKR = 1 indicates a packet has been received 
error-free and in correct sequence according to the received N (S) count. The l-field data 
has been placed in the host's RAM memory. NE is advanced. 



NOTE1: 

The three interrupt-causing bits are SR17, SR16, and 
SR15. Any of the three will cause an interrupt request 
(INTR goes lo w). Af ter SR1 is read, all three bits are 
reset to 0, and INTR returns to high. 



STATUS REGISTER 2 



REGISTER 


SR27 




SR26 


SR25 


SR24 


SR23 


SR22 


SR21 


SR20 


SR2 


T10UT 


IRTS 


REC 
IDLE 














LINK 


BIT 


DESCRIPTION 


SR20 

ST24-21 

SR25 

SR26 

SR27 


If the link is established, LINK = 0. If the link is logically disconnected, LINK = 1 . 

Unused Bits — 0. 

REC IDLE (Receiver Idle) indicates that the WD2511 has received at least 15 contiguous 
1's. 

IRTS stands for the Internal Request-To-Send bit, and indicates that the transmitter is 
attempting (successful or not) to send either data or flags. 

T1 OUT bit means that timer T1 has timed-out. This bit returns to when T1 is re-started. 
When T1 OUT = 1 , T1 is not running. NOTE: This bit could be a 1 for a few microseconds 
in between intervals when T1 stops and is restarted. 



ERROR REGISTER (ERO) 



HEX 
VALUE 


ERROR/EVENT 


02 


Receiver overrun. The Receiver Register (RR) had a character to load into the FIFO but the 
FIFO was full. See note 2. 


04 


Transmitter underrun. The Transmitter (TR) needed a character from the Transmitter Hold- 
ing Register (THR) but the THR was not ready. The frame being transmitted is aborted. See 
note 2. 


10 


RLOOK not ready. REC RDY bit of next segment is but RECR = 1 . This interrupt will not 
occur if RECR = 0. 


21 


Link is up. Was down. 


22 


DISC sent. REC IDLE for time T1 xN2. 


24 


DISC sent. SABM sent N2 times without receiving UA. 


30 


Received DISC or DM while link was up. 


41 


Going to next chain segment. 


42 


Next chain segment of the Receiver was not ready. 


80 


Link reset (SABM) received. 


88 


S-command sent N2 times without acknowledgement. 


CO 


Frame Reject (FRMR) received. See note 1 . 


C1 


Frame Reject (FRMR) transmitted. See note 3. The received C-field (returned in the first 
l-field byte of the FRMR frame) was invalid. 


C3 


Frame Reject (FRMR) transmitted. See note 3. The received and rejected frame contained 
an l-field which is not permitted with this frame type. 


C4 


Frame Reject (FRMR) transmitted. See note 3. Received l-field exceeded the total amount 
of l-field data bytes established in Register C. 


C8 


Frame Reject (FRMR) transmitted. See note 3. The received frame contained an invalid 
N(R). 



o 
ro 
en 



NOTES: 

1 . Whenever a Frame Reject (FRMR) is received, the 
l-field will have been placed in the appropriate mem- 
ory location by the DMA. A link reset (SABM) will be 
transmitted. The NB is not advanced. 

2. Receiver overr un and Transmitter underrun are indi- 
cation that the TC/ RC cloc ks are either too fast for 
the WD2511, or the DACK response is too slow, or 
both. 

3. As a result of FRMR transmitted, a SABM is 
received, causing link reset. In this case, only the 
Frame Reject interrupt is indicated. 

W, X, Y, Z OF FRMR 

A frame reject (FRMR) contains a three byte l-field. The 
first byte is the rejected frame control field. The second 
byte contains the current N(S) and N(R) counts of the 
station reporting the reject condition. The third byte 
contains W-X-Y-Z-0-0-0-0 where W is the LSB. 

W set to 1 indicates that the control field received and 
returned in the first l-field byte was invalid. 

X set to 1 indicates the rejected frame contained an 
l-field which is not permitted with this command. 

W is also set to 1 in this case. 



Y set to 1 indicates the received l-field exceeded the 
maximum l-field data byte count established (CHAIN/ 
BUFFER SIZE). Y is mutually exclusive with W. 

Z set to 1 indicates the received control field contained 
an invalid N(R). Z is mutually exclusive with W. 

Upon receiving a FRMR, the WD2511 will place the 3 
byte l-field in memory by DMA, just as if the FRMR were 
a packet. 

When the WD2511 transmits a FRMR, the frame reject 
condition is entered. Only a received SABM or DISC 
will clear this condition. If any other command is 
received, the WD2511 will re-transmit the FRMR. Also, 
the WD2511 will not transmit packets while in the 
frame reject condition. 

In the FRMR l-field, bit #4 of the second byte is a "1" if 
the rejected frame was a response and a "0" if the 
frame was a command. 

MEMORY ACCESS METHOD 

The WD2511 memory access is accomplished by the 
use of DMA and two look-up tables. These tables are 
set-up to allow up to 7 l-frames to be outstanding in 
each direction of the communications link. The look-up 
tables are divided into a transmit and a receive area 
(TLOOK and RLOOK) and are located in memory exter- 
nal to the WD2511. 



3 

D 
ro 
01 



TLOOK 



RLOOK 



A15 


A14 


A13 


A12 


A11 


A10 


A9 


A8 


A7 


A6 


A5 


A4 


A3 


A2 


A1 


AO 



These tables contain address and control information 
for individual Transmit/Receiver packets. 

To provide the WD2511 access to TLOOK and RLOOK 
load only the starting address of TLOOK into the 
WD2511 registers A and B. 



REG A 
REGB 

A0-A15 16 bit TLOOK starting address 

The TLOOK and RLOOK tables are each divided into 8 
segments and each segment contains 8 bytes. Figure 3 
illustrates the segmentation of TLOOK and RLOOK. 
Figure 5 and 6 illustrate the contents of a single TLOOK 
and RLOOK segment. 

TRANSMIT 

To transmit, the WD2511 will have read from TLOOK 
the starting address and length of the first packet to be 
transmitted. The WD2511 will automatically transmit 



the flag, address, and control fields. Next, the informa- 
tion field data will be transmitted using DMA from the 
"SEND #0 PACKET" memory buffer. At the end of the 
information field, the WD2511 will automatically send 
the FCS and closing Flag. The WD2511 will then move 
on to the next packet. 

If retransmission of one or more (up to seven) packets 
becomes necessary, the WD2511 will automatically 
retrace the previous transmissions through the TLOOK 
table. The user's CPU software does not become 
involved in the retransmission. However, an ERROR 
COUNTER is incremented. (See Error Counter 
Section.) 

RECEIVE 

When received, each frame is checked for correct 
address and FCS fields and for type of control field. If 
the frame is a packet, the information field is placed in 
the assigned memory location in a method similar to 
that used in transmit mode. If the packet is received 
error-free and in proper N(S) sequence count, an inter- 
rupt is generated and the WD2511 is ready for the next 
packet which will be placed in the next location. 

Figure 4 shows a "store-and-forward" example that is 
useful in a network node. 











TSADR #0 












TLOOK^. 


— ~ 


SEND 

PACKET 

#0 


I TCNT 
i #0 




SEGMENT 




( 


SEGMENT 1 


SEGMENT 2 


. ^~~~^^^^. 




TSADR #1 


SEGMENT 3 








^^ TSADR #2 


SEND 

PACKET 

#1 

(FIRST PART) 


LiMy 


SEND 

PACKET #1 

(SECOND PART) 




SEGMENT 4 


SEGMENT 5 


JL 






SEGMENT 6 








RLOOK^. 


TCNT#2 


SEND 
PACKET #2 




XFR ADR 




TCNT #1 IS 


SEGMENT 7 






GREATER THAN 
BUFFER SIZE. THUS, 
SECOND PART 
OF #1 IS 


SEGMENT 








( 


SEGMENT 1 




SEGMENT 2 














RECEIVE 

PACKET #0 

(FIRST BLOCK) 


RSADR#1 


RECEIVE 

PACKET #0 

(SECOND BLOCK) 




SEGMENT 3 




SEGMENT 4 


SEGMENT 5 


XFR ADR 


XFR ADR 


SEGMENT 6 






V 


I 


RECEIVE 
PACKET 

#1 






SEGMENT 7 


LIM 




ERROR 
COUNTERS 




t 




XFR ADR 


F 








igure3. Ml 


EMO 


FtY ACCESS 


SCHEME 











10 




T 

SERIAL 

RECEIVE 

CHANNELA 



After the Data Buffer is received by CH A, the length (RCNT) is 
in RLOOK segment #3. The CPU interrogates the packet header 
(at the beginning of the Data Buffer) and concludes that the 
buffer must be send out of CH B. RSADR, RCNT, and the 
residual information are transferred from #3 segment to next 
available TLOOK segment in CH B which is #6 in this example. 

Figure 4. STOREANDFORWARD EXAMPLE 



WD2511 
CHB 



SERIAL 
TRANSMIT 
CHANNEL B 



3 

a 

IS) 

ai 



TLOOK AND RLOOK 

Figures 5 and 6 detail the individual segments for 
TLOOK and RLOOK. 

BRDY means that the transmit buffer is ready. The 
WD2511 will send the block only after the CPU sets 
BRDY = 1. (BRDY is used in conjunction with the 
SEND bit.) At the completion of the transmission, the 
WD2511 will set BRDY = and then read the BRDY of 
the next segment. 

After transmitting a packet, an acknowledgement must 
be received from the remote device. The acknowledge- 
ment is contained in the received N(R) count of an I- 
frame or S-frame. Upon acknowledgement, the 
WD2511 will set ACK'ED = 1, and generate a block- 
acknowledged interrupt. Before assigning a new block 
to a segment in TLOOK, the CPU must make sure that 
the previous block which used that segment number 
has been acknowledged. 

REC RDY informs the WD2511 that the receive buffer is 
ready. The WD2511 will not receive a packet into a 
buffer referenced by a particular segment until REC 
RDY = 1. If the WD2511 progresses to a segment 
which has REC RDY = 0, an error interrupt will be 
generated. 



After receiving an error-free packet with correct N(S), 
the WD2511 will, in order: 1) Set FRCML (Frame 
Complete), clear REC RDY and store received residual 
count. 2) Store the received length, in characters, of the 
l-field in RCNT HI and RCNT LO. 3) Advance the NE 
count and generate a packet received interrupt. 4) 
Acknowledge the received packet at the first opportu- 
nity. 

The addresses (TSADR and RSADR) are 16-bit binary 
addresses. HI represents the upper 8-bits and LO rep- 
resents the lower 8-bits. The counts (TCNT and RCNT) 
are 12-bit binary numbers for the number of characters 
in the l-field. 

TSADR is the starting address of the buffer to transmit 
and TCNT is the binary count of the number of bytes to 
transmit. (4087 is the maximum value allowed in 
TCNT.) 

RSADR is the starting address of the receive buffer. 
After successfully receiving the packets, the WD2511 
will write the value of RCNT which is the binary length 
of the received packet. 

Whether the WD2511 accesses a look-up table or a 
memory block, a DMA Cycle is required for each 
access. 



11 



a 

10 
ai 





BYTE # IN 
SEGMENT 


7 


6 


5 


BIT# 
4 3 


2 


1 





1 


ACK'ED 


NU 


NU 


NU 


NU 


NU 


NU 


BRDY 


2 


TSADR HI 


3 


TSADR LO 


4 


SPARE 


TCNT HI 


5 


TCNT LO 


6 


SPARE FOR USER DEFINITION 


7 


SPARE 


8 


SPARE 



NU = Not Used 



FIGURE 5. TLOOK SEGMENT 



The control bits in TLOOK (BRDY and ACK'ED) and in 
RLOOK (FRCML and REC RDY) define various states 
for each segment. These states are shown below: 

TLOOK STATES 



ACK'ED 


BRDY 


STATE 




1 
1 


1 


1 


Ready To Transmit (CPU set BRDY, cleared ACK'ED) 
transmitted and Awaiting Acknowledge (WD2511 cleared BRDY) 
Received Acknowledge (WD2511 set ACK'ED) 
This state not allowed 



'State 0-0 could also occur whenever there is no data ready to send. 



BYTE # IN 
SEGMENT 


7 


6 


5 


Bl 
4 


■# 
3 


2 


1 





1 


FRCML* 


NU 


NU 


NU 


RES2 


RES1 


RESO 


REC 
RDY 


2 


RSADR HI 


3 


RSADR LO 


4 


NOT USED 


RCNT HI 


5 


RCNT LO 


6 


SPARE FOR USER DEFINITION 


7 


SPARE 


8 


SPARE 



NU = Not Used (NOTE: The "not used" bits may be either 1 or 0). 
*FRCML = Frame Complete 

FIGURE 6. RLOOK SEGMENT 



12 





CPU ^" 

CLEARS 
^-'ACK'ED 








CPU SETS 
BRDY 






I NO DATA \ 
=p TO SEND Kv^ 
-"-"^ \ 0-0 / 


Z 




CPU CLEARS ACK'ED 
AND SETS BRDY 


D 


( RECEIVED Y- 
ACKNOWLEDGE 1 


READY TO \ 
SEND 
0, ) 


ai 


V 1 - £ 






WD2511 CLEARS 
^^ BRDY 


-*- 


WD2511SETS 
ACK'ED 


/ DATA HAS BEEN \ 
J SENT WAITING 
"~1 FOR ACKNOWLEDGE 

\ °"° / 







TLOOK SEGMENT STATE FLOW 



Notice that in a TLOOK segment, the 0-0 state could 
have two meanings. Due to control internal to the 
WD2511 , this will not pose an ambiguity to the WD2511 . 
However, if it is a difficulty to the CPU, the CPU could at 
start-up, set all ACK'ED bits. Since this would only be a 

RLOOK STATES 



start-up procedure, this would not violate the "deadly 
embrace" rule. 

In the "WAITING FOR ACKNOWLEDGE" state, one or 
more re-transmissions could occur. 



FRCML 


REC RDY 


STATE 



1 


1 


1 



1 


Ready To Receive (CPU set REC RDY, cleared FRCML) 
Received Packet (WD2511 set FRCML, cleared REC RDY) 
Not Ready (CPU cleared FRCML) 
This state not allowed 




RLOOK SEGMENT STATE FLOW 



REGISTER 


CHAIN 


BUFFER SIZE 


C 


Bit 

7 


Bit 
6 


Bit 
5 


Bit 
4 


Bit 
3 


Bit 
2 


Bit 
1 


Bit 




CHAINING/BUFFER SIZE 

The WD2511 includes a chained-block feature which 
allows the user more efficient use of memory particu- 
larly in situations where the maximum packet size is 
much larger than the average packet size. 

Register C is used to program the chaining feature. The 
upper 4 bits define CHAIN which is the number of chain 



segments allowed in addition to the first segment. (If 
this feature is not used, make CHAIN all 0's.) 

The lower 4 bits of Register C define the buffer size, 
which is the size of the buffer in multiples of 64 bytes 
including the transfer address (XFR ADR). If buffer size 
is 0000, the size is 64. For 0001, the size is 128, and so 
on. 



13 



a 

to 



The maximum amount of l-field data bytes that can be 
contained in this buffer is the buffer size minus 2 bytes 
(XFR ADR) for all transmitter and receiver chaining 
blocks, except for the last receiver chaining block. For 
this block, the maximum amount of l-field data bytes is 
the buffer size minus 3. 

For example, suppose that the buffer size defines a 
segment size of 128 and that CHAIN defines 8 addi- 
tional segments in addition to the first. (Register C 
would be hex 81 in this example.) When 126 bytes of 
l-field data have been received, the WD2511 will read 
the next two buffer bytes as a transfer address (XFR 
ADR) pointing to another segment. At the end of that 
segment is another XFR ADR, and so on, up to a maxi- 
mum of 9 total segments, (in this example). 

For the receiver, a XFR ADR of all O's will mean that the 
next segment is not ready. If the WD2511 reaches a 
XFR ADR on the receiver with all Os, there will be an 
Error Interrupt code 42. Otherwise, there will be an 
Interrupt code 41 which is a status indication that the 
WD2511 is going to the next segment. I/O Register 6 
upper 4 bits gives a status of which chain segment is 
currently being used. 

The transmitter chaining works like the receiver with 
the following exceptions: 

1. XFR ADR = all O's will not indicate next segment not 
ready. 

2. There is no interrupt when going from one segment 
to another. 

3. There is no status of the current segment being 
used. 

4. Last chaining block is allowed to contain one more 
l-field data byte. 

Total amount of l-field data bytes in receiver = (64 x (1 
+ BUFFER SIZE) - 2)x(1 + CHAIN) - 1. 

The total amount of l-field data bytes in transmitter = 
(64x(1 + BUFFER SIZE) - 2)x(1 + CHAIN). 

Also, note that the transmitter and receiver counts are 
modified by 2 for each time a chain boundary is 
crossed. For example, if BUFFER SIZE = 0001 (seg- 
ment size = 128 bytes including XFR ADR), and if an 
l-field of 270 bytes is to be transmitted, then there will 
be two times that a chain boundary is crossed. The 
TCNT must be made 274 to send 270 bytes. The same 
is true for RCNT Note that the largest block of data that 
can be sent without chaining is 1021 bytes. 

"DEADLY EMBRACE" PREVENTION 

A "deadly embrace" can occur when two processors 
reach a state where each is waiting for the other. In this 
case, the two processors are the user's CPU and the 
micro-controller inside the WD2511. Therefore, to pre- 
vent the "deadly embrace," the following rule is 
obeyed by the WD2511 and should also be obeyed by 
the user's CPU. This rule applies to TLOOK, RLOOK 
and to the I/O registers. The Error Counters do not 
apply to this rule. 



RULE: If a bit is set by the CPU, it will not be set 
by the WD2511, and vice versa. If a bit is 
cleared by the WD2511, it will not be 
cleared by the CPU, and vice versa. 



As an example, the BRDY bit in the TLOOK segments 
is only set by the CPU and only cleared by the WD2511 . 

SEND BIT CONTENTION 

The WD2511 may be clearing the Send bit when the 
host is setting it. To insure that the bit is set the host 
should read the status of the Send bit after it is set. If 
the Send bit is cleared the host should set it again. 

TLOOK AND RLOOK POINTERS 

There are three 3-bit counters for the status of the seg- 
ments in TLOOK and RLOOK. Status Register #0 
(SR0) contains counters NA and NB which are used in 
conjunction with TLOOK. NB is the segment number of 
the next block to be transmitted and is advanced at the 
end of each block transmission. NA is the value of the 
segment of the next block to be acknowledged. If all 
transmitted blocks have been acknowledged, then NA 
= NB. 

In SR1 is a 3-bit counter, NE, used in conjunction with 
RLOOK. NE is the value of the segment number where 
the next received packet will be placed. 

NA = Next to be Acknowledged 

NB = Next Block to be Transmitted 

NE = Next Expected to be Received 

VARIABLE BIT LENGTH 
AND RESIDUAL BITS 

The WD2511 will only send 8 bits per character and all 
transmitted frames will have an integral number of 
bytes. 

The WD2511 may receive a packet with, or without, an 
integral number of bytes. The "RES" bits in the 
RLOOK tables indicate the number of received resid- 
ual bits. The residual bits occupy the lower portion of 
the last received character. 



RES 2 


RES1 


RES0 


Received Residual Bits 




















1 


7 





1 





6 





1 


1 


5 


1 








4 


1 





1 


3 


1 


1 





2 


1 


1 


1 


1 



14 



ERROR COUNTERS 

Following contiguously after RLOOK are six 8-bit error 
counters. The WD2511 will increment each counter at 
the occurrence of the defined event. However, the 
WD2511 will not increment past 255 (all 1 's). The CPU 
has the responsibility of clearing each counter. The first 
counter past RLOOK is #1, etc. 



ERROR 
COUNTER 


TYPE OF ERROR 


1 


* Received Frames with FCS Error 
(includes frames ABORTed in the 
l-field). 


2 


Received Short Frames (less than 
32-bits) 


3 


** Number of times T1 ran-out 
(completed) 


4 


Not used 


5 


*REJ Frames Received 


6 


REJ Frames Transmitted 



These counters are incremented only if the received 
A-field is equal to either Register E or F. 
** Incremented only when attempting to transmit a 
command. 

The Error Counters are accessed by the WD2511 trans- 
mitter DMA channel. Therefore, if multiple errors are 
received while the WD2511 is transmitting a long frame, 
only the last error will be counted. The only Counters 
which could miss counts because of this are Counters 
#1, #2, and #5. The error Counters are incremented 
only when the link is up (LINK = 0). 



OTHER I/O REGISTERS 
RECEIVED C-FIELD 

Register 7 is the C-field of the last received frame, pro- 
vided the A-field of the frame was equal to either regis- 
ter E or F, the FCS was good, the frame contained 32 or 
more bits, and the WD2511 is not waiting for a SABM or 
DISC in response to a transmitted FRMR. 

TIMER 

Registers 8 and 9 define a 10-bit timer (T1), and a 6-bit 
Maximum Number of Transmissions and Retransmis- 
sions counter (N2). 



REGISTER 


BIT* 


7 


6 


5 


4 


3 


2 


1 





8 






T1 




LSB 


9 


MSB 


N2 




LSB MSB 





MSB = Most Significant Bit 
LSB = Least Significant Bit 

T1 provides the value of a delay in waiting for a 
response and/or acknowledgement. The delay is the 
binary count multiplied by time CT where: 

, 16384 

CT = ~cTK~ sec 

Thus, if CLK = 1 MHz, then T1 may be set in incre- 
ments 16.384 milliseconds, to a maximum delay of 
16.78 seconds. All ones in T1 is maximum delay. 

Once the CPU establishes T1 and N2, there is no need 
to write into T1 and N2 again unless a master reset 
(MR) has occurred, there is a power loss, or the CPU 
needs to change T1 or N2. If a time-out occurs, the 
WD2511 will still retain T1 and N2. 

The conditions for starting, stopping, or restarting T1 
are shown below: ("Re-start" means starting T1 before 
it ran-out). 



3 
O 
io 

01 



START T1 


RE-START T1 


STOP T1 


1 . * l-f rame sent and T1 not already 

in progress due to previous I- 
frame. 

2. — 

3. *SABM or DISC sent. (N2 

restarted at first occurrence) 

4. Receiver Idle (REC IDLE = 1 ) 

5. S — command sent 


*Acknowledgement received 
to some, but not all, l-frames. 

*RNR received while link up. 

* Frame sent, while REC IDLE 
= 1 


Acknowledgement received 
for all l-frames. 

UA or DM Received 
Detected REC IDLE = 



*N2 is restarted. 



"A" FIELD REGISTERS 

Registers E and F provide a programmable A-field. 
This allows the WD2511 to be a super-set of the X.25 
document. That is, the WD2511 can handle a wider 



range of application than the DTE-DCE links defined 
in X.25. These wider ranges include: DTE-to-DTE con- 
nection, multipoint, and loop-back testing. 



15 



o 

IS) 

oi 



If the WD2511 is strictly in an X.25 DTE-DCE link, use 
the values shown below: 

DTE Register E = 01 

Register F = 03 

DCE Register E = 03 

Register F = 01 

If performing a loop-back test, either internal (CR03 = 
1) or external (CR03 = 0), registers E and F should be 
the same. 

V. LAPB PROCEDURE 

The Link Access Procedure Balanced (LAPB) is 
described in CCITT Recommendation X.25 as the 
Level 2 protocol for the Asynchronous Balanced Mode 
(ABM). 

Zero bit insertion/deletion, use of flags, and FCS are 
part of Level 2, and have been discussed in this docu- 
ment. 

The DTE is the Data Terminal Equipment and the DCE 
is the Data Circuit Termination Equipment (the network 
side of the DTE-DCE connection). 

The DTE and DCE are each "combined" stations in 



that each can transmit and receive commands and 
responses. Whether a particular frame is to be taken 
as a command or a Response is determined by the con- 
tents of the address field. Commands from the DCE and 
the associated responses from the DTE use address 
A (hex 03). 

Commands from the DTE and the associated 
responses from the DCE use address B (hex 01). 

The individual commands and responses are shown in 
Figure 7. 

USE OF POLL BIT 

One use of the Poll bit (P) is in conjunction with Time- 
Out Recovery. Timer T1 is started at the beginning of a 
transmitted command provided it has not been previ- 
ously started. If T1 runs out, the command will be 
retransmitted with P = 1 . If T1 runs out again, the com- 
mand will again be retransmitted, with P = 1 up to N2 
times. At N2 + 1, an error interrupt will occur. If the 
command was an S-frame (originally an l-frame), the 
WD2511 will reset the link by transmitting a SABM. If 
the command was a SABM, the WD2511 will send a 
DISC. If a DISC, the WD2511 will continue to send a 
DISC indefinitely. 



LAPB Commands and Responses (Bit is transmitted first). 
Only the FRMR and l-frame contain l-fields. 



FRAME TYPE 


COMMAND 


RESPONSE 


BIT# 


INFORMATION 
(I) 


l-FRAME 
(PACKET) 




7 6 5 


4 


3 2 1 





N(R) 


P 


N(S) 





UNNUMBERED 
(U) 


SABM 




1 


P 


1111 


DISC 




1 


P 


11 




UA 


1 1 


F 


11 




FRMR 


1 


F 


111 


DM 





F 


1111 


SUPERVISORY 
(S) 


RR 


RR 


N(R) 


P/F 


1 


RNR 


RNR 


N(R) 


P/F 


10 1 


*REJ 


REJ 


N(R) 


P/F 


10 1 



The WD2511 will not send a REJ command (will send REJ response, only), but may receive either a REJ command 
or REJ response. 

FIGURE 7. 



16 



TRANSMISSION OF ABORT 

An ABORT (seven contiguous 1 's) is transmitted to ter- 
minate a frame in such a manner that the receiving sta- 
tion will ignore the frame. There are two conditions 
which will cause the WD2511 to transmit an ABORT: 

1 . Transmitter Under-Run 

2. While transmitting a packet, a REJ is received. 

LOOP-BACK TEST 

The loop-back may be internal (CR03 = 1) or external 
(CR03 = 0). Of course, if external, RD and TD must be 
tied together either directly or remotely. 

If CR03 = 1 , TD is internally tied to RD, and the RD sig- 
nal (pin 16) is internally disconnected. Also, TC is inter- 
nally tied to R C and the pin at RC (pin 17) is internally 
disconn ected . CTS must be connected externally to 
GND or RTS. 



WD2511 ELECTRICAL SPECIFICATIONS: 

ABSOLUTE MAXIMUM RATINGS: 

Voltages referenced to Vss 

High Supply Voltage (Vqd) - 0.3 to + 15V 

Voltage at any Pin -0.3to + 15V 

Operating Temperature Range 0°C to + 70°C 

Storage Temperature Range .... - 55°C to + 125°C 

NOTE: 

Maximum limits indicate where permanent device 
damage occurs. Continuous operation at these limits is 
not intended and should be limited to those conditions 
specified in the DC Electrical characteristics. 



O 

IN) 

Ol 



Operating DC Characteristics: Vss = 0V, V CC = 


+ 5.0V ± 


0.25, Vss 


= + 12.0V ±0.6VTa 


= 0°to +70°C 


SYMBOL 


PARAMETER 


MIN 


TYP 


MAX 


UNIT 


CONDITIONS 


IDD 


Vqd Supply Current 




20 


70 


mA 




ice 


Vqc Supply Current 




200 


280 


mA 




VDD 


High Voltage Supply 


11.4 


12 


12.6 


V 




vcc 


Low Voltage Supply 


4.75 


5 


5.25 


V 




V|H 


Input High Voltage 


2.4 






V 




V|L 


Input Low Voltage 






0.8 


V 




VOH 


Output High Voltage 


2.8 






V 


lO = -0.1mA 


VOL 


Output Low Voltage 






0.4 


V 


lO = 1.6mA 


"LH 


Input Source Current 






10 


^ 


Vin = Vcc 


ill 


Input Sink Current 






10 


mA 


Vin = +0.4V 


lOZH 


Output Leakage (High 
Impedance) 






50 


^ 


Vin = Vcc 


lOZL 


Output Leakage (High 
Impedance) 






50 


mA 


Vin = +0.4V 



17 



AC Timing Characteristics (AC): 



SYMBOL 


PARAMETER 


MIN 


TYP 


MAX 


UNIT 


CONDITIONS 


CLK 


Clock Frequency 


0.5 




2.05 


MHz 


Notel 


RC 


Receive Clock Range 









MHz 


Note 4 


TC 


Transmit Clock Range 









MHz 


Note 4 


MR 


Master Reset Pulse Width 


10 






mS 




TAR 


Input Address Valid to RE 









nS 




trd 


Read Strobe (or DACK 
Read) to Data Valid 


2 




375 


nS 


Note 5, 2 


thd 


Data Hold Time from Read 
to Strobe 


20 




100 


nS 




tha 


Address Hold Time from 
Read Strobe 









nS 




Taw 


Input Address Valid to 
Trailing Edge of WE 


100 






nS 




Tww 


Minimum WE Pulse Width 


200 






nS 




tdw 


Data Valid to Trailing Edge 
of WE or Trailinq Edqe of 
DACK for DMA Write 


100 






nS 


Note 2, 3 


TWRR 


CS High between Writes 


300 






nS 




TRDR 


CS High between RE 


300 






nS 




Trr 


RE Pulse Width 


375 






nS 




tdak 


DACK Pulse Width 


375 










tahw 


Address Hold Time after 
WE 


80 






nS 




tdhw 

TDA1 

tdao 


Data Hold Time after WE or 
after DACK for DMA Write 


100 




80 
375 


nS 
nS 


Note 3 
Note 5 


Time from DRQO (or DRQI) 
to Output Address Valid if 
ADRV = 1 


Time from DACK to Output 
Address Valid if ADRV = 


tdd 


Time from Leading Edge of 
DACK to Trailinq Edqe of 
DRQO (or DRQI) 






375 


nS 


Note 5 


tdah 
tdmw 


Output Address Hold Time 
from DACK 


20 
20 




100 
100 


nS 
nS 


Note 2 


Data Hold Time from DACK 
for DMA Out 


ttdv 


TD Valid 


100 






nS 




TSRD 


RD Setup 









nS 




THRD 


RD Hold 


320 






nS 





NOTES: 

1 . Clock must have 50% duty cycle. 

2. Th ere mu st not be a CPU read or write (CS-RE or CS-WE) within 500 
of DACK. 



3. There must not be t he leading (falling) edge of DACK allowed within 
CPU write (CS-WE). 

4. See "Ordering Information" for maximum serial rates. 

5. C(load) = 100pf 

6. Measured by discharging a 100pf capacitor to each pin through a 1 K ohm resistor. 



nanoseconds after the trailing (rising) edge 
500 nanoseconds after the completion of a 



18 



IA0-IA3^" 



RE 
DAL0-DAL7 



T 



U-Tar-^ 



- T RR- 



X 



z/. 



T HA 



/ DATA \ 
K VALID S . 



V 



| \ VALID X . 

U t rd — *\*\ Thd r*~~ 



IA0-IA3 



X 



X 



N ~ 



- T AW- 
- T WW- 



- T DW- 



< 



^j [^-Tahw 

VALID ") 



—*n T DHW p— 



o 

10 
01 



CPU READ (CS IS LOW) 



CPU WRITE (CS IS LOW) 



A0-A15. 



(ADRV = 0) 



-*| TDD fc 



— *>l T DA 1 (-*- *^ [*-' 



> 



A0-A15 
(ADRV = 1) 



DACK 
DAL0-DAL7 



T DAK 



\ 



T DAH 



X 



T DMW 



L 



< 



> 



Trd- 



DRQI- 



(A0-A15 SAME AS DMA OUT) 
|^- T DD-»-| 



S 



|>* T DAK ■ 



\L 



< 



Tdw |Tdhw] 

k VI 



DATA VALID 



> 



DMA OUT 



DMA IN 




TD-RD TIMING 

Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital Corporation for 
its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any 
patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change specifications at anytime without notice. 



19 



APPENDIX A 

TRANSPARENT MODES 

The WD2511 was originally intended to be a link level 
controller meeting the requirements of X.25 LAPB and 
this has been accomplished. However, there has been 
an increasing demand from potential WD2511 users for 
additional frame types not included in the LAPB frame 
type repertoire. 

For example, the Bell System standard, BX.25, calls for 
the use of XID (exchange identification) in LAPB con- 
nections of DTE-to-DTE and in Dial access. (Of course, 
DTE-to-DTE and Dial access are not X.25 in the strict- 
est sense.) Also, Western Digital has received several 
requests for the use of a SIM (set initialization mode). 
Also, there has been one request to allow "unknown" 
frames to pass thru the chip for the purpose of 
teleloading. 

Therefore, we have added two selectable modes to the 
WD2511 : transparent transmit and transparent receive. 
Basically, these two modes allow the user the option to 
pass certain non-LAPB frames thru the chip without 
controlling these frames according to the LAPB 
protocol. 

FEATURES OF THE TRANSPARENT MODES 

• May transmit any A and C field under transparent 
control. 

• May receive any U-frame not part of the LAPB reper- 
toire if transparent-receive enabled. 

• Transparent modes are link state independent. 

1.0 HOW THE TRANSPARENT MODES WORK 

Two control bits have been added. TXMT (CR17) is the 
bit to enable the Transparent Transmit and TRCV 
(CR16) will enable the Transparent Receive. 

1.1 TRANSPARENT TRANSMIT 

When TXMT = 1, the WD2511 will transmit the frame in 
the next TLOOK segment provided SEND (CR10) = 1 
and BRDY of that TLOOK segment is 1 . The link may 
be either UP or DOWN. The WD2511 will not add the A 
and C fields to the Transparent Transmitted frame. The 
user's CPU must add these fields as the first two bytes 
in the transmit buffer. Thus, the significance of the 
transmit count (TCNT) is different from normal packet 
transmission. In packet transmission, TCNT is the 
count of the l-field. In transparent transmission, TCNT 
is the l-field plus the A and C fields (l-field plus two 
bytes). 

The timer, T1, will be disabled in transparent transmis- 
sion. Therefore, if using this feature while the link is UP, 
it is advised that TXMT be set only when there are no 
outstanding (unacknowledged) packets which is indi- 
cated whenever NA = NB. 



At the end of the transparent transmission, there will be 
an interrupt with XBA = 1. The SEND bit will be 

cleared, but the BRDY bit will not be cleared. The NB ^ 

pointer will not be incremented. To send another trans- O 

parent frame, set SEND. To resume packet transmis- £j> 

sion, clear TXMT and set SEND. (Of course, the -j. 

TLOOK segment must be set-up prior to setting SEND.) "^ 

If SEND is set while the link is down, a transmission will 
occur even if TXMT = 0. Under this condition, a packet 
will be transmitted from current TLOOK segment, NB 
and V(S) will be incremented, and the chip will go on to 
the next TLOOK segment just as if the link were UP. 
However, the WD2511 will expect no acknowledgment 
to the packet(s). If the link is brought UP later, NB and 
V(S) are cleared to at the time the link comes UP. 

The bit XI (CR15) is used only when TXMT = 1. XT 
stands for Transmit l-field. If the frame contains three, 
or more bytes, not counting FCS, set XI = (XJf the 
frame contains two bytes not counting FCS, set XI = 1. 
When XI = 1, only two frame bytes will be transmitted 
regardless of TCNT. DO NOT attempt to transmit a 
frame with TXMT = 1 and XI = if TCNT is 2, 1 , or 0. 

1.2 TRANSPARENT RECEIVE 

For the purposes of this discussion, it is necessary to 
define an "unknown frame!' That is, a frame which is 
"unknown" to the WD2511 . 

Unknown Frame: A U-frame (unnumbered) frame 
which is not part of the LAPB repertoire. The U-frame 
repertoire in LAPB is SABM, DISC, DM, UA, and 
FRMR. For the purposes of this discussion, "UF" will 
refer to an unknown frame without an l-field, and "UFI" 
will refer to an unknown frame with a l-field. 

A received SREJ (Selective REJect), which is an S- 
frame, is not considered an unknown frame by the 
WD2511 . If the link is DOWN and an SREJ command is 
received, a DM response will be sent. If the link is 
DOWN and a SREJ response is received, the SREJ is 
disregarded. If the link is UP and a SREJ command or 
response is received, a FRMR will be sent with W = 1 . 
The WD2511 will treat a received SREJ the same 
whether TRCV is or 1 . 

A received packet (l-frame) response is not considered 
an unknown frame by the WD2511 . If the link is DOWN, 
the frame is disregarded. If the link is UP, a FRMR will 
be sent with W = 1 and X = 1 . The received packet 
response is treated the same whether TRCV is or 1 . 

Whether TRCV is or 1, the WD2511 will check all 
received frames to insure that the A-field equals either 
Register E or F, that the FCS is correct, and that the 
frame contains 32 bits or more. If TRCV = 0, and if a UF 
or UFI is received, and if the link is UP, the WD2511 will 
send a FRMR with W = 1 (W and X are 1 in the case of 
a UFI). See "States of the WD2511" 

When TRCV = 1, the WD2511 will be enabled to 
receive all frames. If the frame is "known" by the 
WD2511, it will be treated according to the protocol just 
as if TRCV = 0. However, if the frame is a UF or UFI, it 
will be passed on to the user's CPU. 



21 



3 

o 

10 
01 



When an unknown frame is received while TRCV = 1, 
there will bean interrupt with ERROR = 1 and the Error 
Register (ERO) will contain one of the following hexide- 
cimal values: 



ERO 


FRAME RECEIVED 


60 
61 
62 
63 


UFI Response 
UFI Command 
UF Response 
UF Command 



TheC-field of the received frame is contained in Regis- 
ter #7. If the frame had an l-field, the frame will be 
placed in the next RLOOK segment and the value of 
RCNT will represent the count of bytes in the l-field (not 
including the A and C fields). The RLOOK pointer, NE, 
will be incremented. Therefore, the relationship 
between NE and V(R) will not be guaranteed if trans- 
parent receive is used while the link is UR However, this 



will not cause a sequence problem in the protocol since 
the actual V(R) is maintained in an internal register in 
the WD2511. Note that NE is cleared when the link is 
brought UR Thus, if transparent receive is used only 
when the link is DOWN, then NE will be equal to V(R). 

A word of caution. If the next RLOOK segment is not 
ready when a UFI is received, the Error Register (60 or 
61) will be overwritten almost immediately with an error 
code 10 (RLNR) and the user will not know if the 
received UFI was a command or response. 

If RECR is set while the link is DOWN, the WD2511 will 
prepare to receive l-fields, whether TRCV is or 1 . If a 
packet command is received, there will be a PKR inter- 
rupt, and the NE and V(R) will be incremented. Of 
course, NE and V(R) are cleared once the link is 
brought up. 

The following tables show what action the WD2511 will 
take when various frames are received. 



TABLE 1 . PACKET RECEIVED (command, not response) 



LINK 



RLOOK READY 



TRCV 



ACTION BY WD2511 



DOWN 
DOWN 

UP 
UP 



NO 


0or1 


YES 


0or1 


NO 


0or1 


YES 


0or1 



DISREGARD 

If N(S) = V(R), PKR interrupt, V(R) and NE 
incremented. No ack transmitted. If N(S) not 
= V(R), DISREGARD. 

If N(S) = V(RT), RNR sent, Else, REJ condi- 
tion entered. 

If N(S) = V(R), PKR interrupt, V(R) and NE 
incremented. Acknowledgement sent at 
next opportunity. If N(S) not = V(R), enter 
REJ condition. 



TABLE II. UFI RECEIVED 



LINK 


RLOOK READY 


TRCV 


ACTION BY WD2511 


DOWN 


NO 


0or1 


DISREGARD 


DOWN 


YES 





DISREGARD 


DOWN 


YES 


1 


Error interrupt 60 or 61 . NE incremented. 


UP 


NO 





FRMR sent. W = 1 X = 1 


UP 


NO 


1 


DISREGARD 


UP 


YES 





FRMR sent. W = 1 X = 1 


UP 


YES 


1 


Error interrupt 60 or 61 . NE incremented. 



If TRCV = 1 and UF (no l-field) is received, there will be 
an Error interrupt 62 or 63, independent of the link state 
or the readiness of RLOOK. 

Of course, the received C-field of any frame will be in 
Register #7 provided the A-field matched either Regis- 
ter E or F, the FCS was good, and the frame contained 
32, or more, bits. 



22 



APPENDIX B 

HALF DUPLEX OPTION ^ 

The WD2511 is basically a full duplex device. The J^ 

receiver is maintained in an "always ready" condition in 

even if the receive buffer is not ready. Thus, whether ^ 

the received frame came from a full or half duplex sys- 
tem is of no consequence to the WD2511 . 

Therefore, the half duplex option affects only the 
WD2511 transmitter. Half duplex is enabled when H/F 
(CR05) = 1 . 

The WD2511 will transmit one frame at a time accord- 
ing to the following procedure: 

A. Enable RTS (RTS goes low). 

B. Wait for CTS (CTS input goes low). 

C. Transmit frame (when CTS is active). 

D. Remove RTS (RTS goes high 2V2 bits of time after 
the last of the trailing flag.) 

NOTES: 

The leading flag will be tra nsmitted somewhere 
between 5 and 13 bits after CTS goes low. 

Interframe fill will be all 1 's (IDLE). 

If T1 is internally activated it is started when RTS goes 
low. 

After RT S goe s low, the frame will not begin transmis- 
sion until CTS goes low. After the frame has started , the 
transmission of that frame is completed even if CTS 
returns high during the frame. 



23 



APPENDIX C STATE DESCRIPTIONS 



LINK DOWN 



IO 
Ol 




CTO STATE N 
TABLE I J 

COLUMN 1 ^J 



SEND 
SABM 



(TO STATE \ 
TABLE I J 

COLUMN 2 1 



SEND 
UA 


-V 


1 


' 


X, 


( TO LINK-UP 1 
V FLOW J 


LINK 

IS 

NOW UP 



SEND IDLE. 
RECEIVER 
IGNORED. 



SABM 



SEND DM 





CLEAR 

SEND 

BIT 



SEND 

TRANSPARENT 

FRAME 




TRANSPARENT 
RECEIVE 



24 



CONDITION FOR RESET OR DISCONNECT 
LINK IS UP 



LINK GOES UP 
FROM STATE TABLE I 



( ENTER J 



INTERRUPT 
21 = ERO 



REC'ED 
DM 



SOFTWARE 
DISCONNECT 



MDISC 
CROO 






INTERRUPT 
ERO -80 



CLEAR 
NE, ETC 
SEND UA 



©- 




CTO STATE ^ S ~~~~ \ 

™f J ( LInTdO^VN ) 



INTERRUPT 
ERO - 88 



Y 




INTERRUPT 




CLEAR 






ERO — 30 


-0Pg 


NE, ETC 








' 


' 




Y 


INTERRUPT 
ERO - 30 










SENDUA 






' 


' 




/^V 


CLEAR 
NE, ETC 




^ 


I) 


26 


' 






' 








' 




s ' 























fc 
*" 



INTERRUPT 
ERO = CO 



jT TO STATE A 

*"V TABLE 2 J 





NEED 

TO RESET 

LINK 




RED'ED 
FRMR 




25 



a 

IN) 

01 



STATE TABLE I 

LINK DOWN, BUT GOING UP 

(Column 2 also applies to link reset) 
ACTION BY WD2511 



STIMULUS: 


COLUMN 1: 

DISC sent. Waiting for UA or DM. 


COLUMN 2: 

SABM sent. Waiting for UA. 


T1 runs out 


Re-send DISC. P = 1 . 


Re-send SABM. P = 1 . 


T1 and N2 run out 


Re-send DISC. P = 1 . 


Send DISC. Interrupt ERO = 24. Go 
to column 1 


Received UA 


Send SABM. Go to column 2 


Clear NA, NB, NE, V(R), V(S). Go to 
link up flow. 


Received DISC 


Send DM. 


Send DM. 


Received SABM 


Disregards 


Send UA. Clear NA, NB, NE, V(R), 
V(S). Keep waitiing for UA. 


Received DM 


Send SABM. Go to column 2. 


Send DISC. Go to column 1 . 


Received something 
other than U A, DM, 
DISC, or SABM 


Disregard. 


Disregard. 



STATE TABLE II 

LINK GOING DOWN (WAS UP) 

User sets MDISC, Chip sends DISC. 



ACTION BY WD2511 




STIMULUS 


DISC sent. Waiting 
for UA. 


T1 runs out 


Re-send DISC. P = 1. 


Received U A or DM 


Go to Link Down Flow 


Received SABM 


Disregard 


Received DISC 


Send DM. Go to Link 
Down Flow 


Received something 
other than DISC, 
SABM, UA, or DM 


Disregard. 



USE OF FLAGS BY THE WD2511 

Once MDISC has been reset the WD2511 will send 
interframe flags (hex 7E) if full duplex is selected (CR05 
= 0) (point ST of the Link Down Flow point has been 
entered). If half duplex is selected, (CR05 = 1), 
interframe fill will be all 1 's (IDLE). 

The WD2511 does not require the interframe time fill 
flags. Either idle or flags will be accepted. However, if 
the receiver detects idle for time T1 X N2, the WD2511 
will send a DISC. 

When sending continuous flags, the WD2511 will send: 

011111100111111001111110011. . . 

The WD2511 will accept either the above sequence as 
continuous flags, or the "shared zero" pattern: 

011111101111110111111011111. . . 



DEFINITIONS OF COMMAND AND RESPONSE 

A transmitted or received command or response is a 
frame with the A-field defined below: 



FRAME 


A-FIELD = 


Transmitted Command 
Received Command 
Transmitted Response 
Received Response 


Register E 
Register F 
Register F 
Register E 



For non-transparent transmitted frames, only com- 
mands or responses are transmitted. A transparent 
transmitted frame (TXMT = 1) may have any A-field the 
user chooses. 

All received frames must be either commands or 
responses or the frame is disregarded ("thrown 
away"), even if transparent receive is enabled (TRCV 
= 1). 



26 



STATE TABLE III 

SENDING l-FRAMES (PACKETS) AND S-COMMANDS 

NOTES: 

In all subsequent pages, the link is considered Up (LINK = 0) unless otherwise stated. X = don't care. TXMT = Ofor 
Table III. 



SEND 


BRDY 


NAANDNB 


RNRR 


T.1 EXPIRES 


RCVD REJ 


ACTION BY WD2511 


1 





X 





No 


No 


Clear SEND (CR10) 


1 


1 


X 





No 


No 


Send next packet with 
N(S) = NB. After trans- 
mission complete. Incre- 
ment NB. Exception: If 
NB + 1 = NA, do not send 
next packet. There are 7 
outstanding. 


X 


X 


X 


1 


Yes 


No 


Send S-command, P = 1 . 


X 


X 


not = 


X 


Yes 


No 


Send S-command, P = 1 . 


X 


X 


not = 


X 


No 


Yes 


Make NA = received N(R). 
Start sequential retransmis- 
sion of packets beginning 
with N(S) = NA. See Note 3. 



o 

io 
oi 



NOTES ON STATE TABLE III 

1 . Received S-frames in Table III are assumed to have 
valid N(R)'s. 

2. When an acknowledgement of one or more previ- 
ously transmitted packets is received, NA is set 
equal to the received N(R). All TLOOK segments 
from the old value of NA up to N(R) — 1 are acknowl- 
edged and the appropriate ACKED bits in the 
TLOOK segments will be set. After setting the 
ACKED bits, an XBA interrupt is generated. 

3. Assuming appropriate TLOOK segments are ready, 
packets are transmitted sequentially with- 
out waiting for an acknowledgement, with three 
exceptions: 

a. There are already seven outstanding (unac- 
knowledged) packets (NB + 1 = NA). 

b. The remote station has indicated a busy condi- 
tion by sending an RNR frame (RNRR). T1 is 
started and an S-command will be transmitted 
with P = 1 when T1 expires. 

c. T1 expired and there are one or more outstand- 
ing packets. An S-command will be transmitted 
with P = 1 . 

4. If an S-frame command is received, the WD2511 
will transmit an S-frame response at the next 
opportunity. 

5. If SEND = and TXMT = 1, a frame will be transmit- 
ted from the next TLOOK segment if BRDY = 1 . 
After transmission, SEND is cleared by the WD2511 . 

RECEIVING AND TRANSMITTING A NULL PACKET 

If an error-free (FCS good) packet is received with a cor- 
rect N(S), but has no l-field, that packet will be treated 
the same as a packet with an l-field. The fact that there 
was no l-field is shown by RCNT equal to all 0's. 



The WD2511 will not transmit a null packet. TCNT must 
not be allowed to be all 0's. 

SENDING A REJ (RESPONSE) 

1 . The REJ condition is entered anytime an error-free 
packet is received with an out-of-sequence N(S). 
Exception: If the received N(S) + 1 = V(R), then the 
received N(S) has been acknowledged, and either 
an RR or RNR is transmitted. 

2. When the REJ condition is entered, the REJ frame 
with N(R) = V(R) is transmitted immediately if a 
packet is not being transmitted, or, at the completion 
of the current packet. There are two exceptions, as 
noted in 3 and 4 below. 

3. If a link resetting SABM needs to be transmitted, the 
SABM is sent. When the UA is received for the 
SABM, the REJ condition is cleared. 

4. If the receiver is not ready (RNRX = 1), the REJ is 
not sent. 

5. Once the REJ condition is entered, only one REJ will 
be transmitted. Another REJ is not transmitted 
unless the REJ condition is cleared and re-entered. 
The REJ condition is cleared if a packet is with cor- 
rect N(S) if a SABM is received, or if a SABM is trans- 
mitted and a UA received. 

6. When the REJ is transmitted, error counter #6 is 
incremented. 

RECEIVING A REJ (RESPONSE OR COMMAND) 

Suppose a REJ has been received error-free with no 
l-field, then: 

1 . If the N(R) is not valid, an interrupt is generated with 
ERO = C8, and a FRMR is transmitted. 



27 



o 



2. If the N(R) is valid, and greater than NA, at least one 
transmitted packet is acknowledged. The appropri- 
ate ACKED bits in TLOOK are set and an XBA inter- 
rupt is generated. 

3. If the N(R) is valid and less than NB, the WD2511 will 
begin sequential retransmission starting with V(S) 
= received N(R). If a packet is being transmitted 
when the REJ was received, that packet is aborted. 
If the N(R) is valid and equal to NB and a packet is 
being transmitted, that packet (which will be #NB) is 
aborted and retransmission will begin. 

4. If the N(R) is valid and equal to NB and there is no 
packet being transmitted, there is no retransmission 
initiated. In this case the REJ has the same effect as 
anRR. 

5. If in 2, 3, or 4 above, the received REJ is a command, 
the WD2511 will transmit a RR or RNR response at 
the next respond opportunity. 



STATE TABLE IV 

LOCAL STATION BUSY (SENT RNR: RNRX = 1) 



DEFINITION OF VALID RECEIVED N(R) 

Reference 

CCITT Recommendation X.25 paragraphs 2.4.10 and 
2.3.4.10. 

Definition 

A valid received N(R) is greater than or equal to NA, 
and less than or equal to NB. 

1. The "greater than" and "less than" relationships 
must be understood in a circular sense. could be 
greater than 7 depending on the values of NA and 
NB. 

2. IfNA = NB, there is only one possible valid received 
N(R), N(R) = NA. 

3. If NB + 1 = NA, there are seven outstanding pack- 
ets and any received N(R) will be valid: N(R) = NB 
ACK's all of the outstanding frames, N(R) = NA 
ACK's none of them, and an N(R) in between ACK's 
some of the packets. 

4. Basically, a received N(R) which is not valid is one 
which acknowledges a packet, or packets, never 
transmitted. 



LINK 


RECR 


REC RDY 


ACTION 


1 


X 


X 


No S-frame transmitted when link down. 


1-0 


1 


1 


RLOOK ready. No RNR frame sent. 


1 -0 


1 





RNR response sent immediately after link 
Up. RNRX set. RLNR Interrupt 


1-0 





X 


RNR response sent immediately after link 
Up. RNRX set. No RLNR interrupt 





1 


1 


Receiver ready to accept packets. 





1-0 


1 


Receiver ready to accept packets. 





1 





RNR response sent. RNRX set. RLNR Inter- 
rupt. 





0-1 


1 


If RNRX was set, then RNRX will be cleared 
after the next received packet or S-com- 
mand. After that, an RR or REJ response is 
sent. 











RNR response sent. RNRX set. There is no 
RLNR interrupt. 



NOTES ON STATE TABLE IV 

1 . The arrows (— ) indicate a change in state from the 
value on the left to the value on the right. 

2. The RNRX status bit is set at the time the receiver- 
not-ready condition was established. The RNR 
frame will be sent immediately if no packet is being 
sent or after the end of the current packet. 

3. When a received packet is brought into memory with 
RNRX = 0, the packet will be accepted provided the 
FCS and N(S) are correct and the l-field is not too 
long. The N(R) may or may not be correct but is 
checked separately. If N(R) is not valid, a FRMR is 
transmitted. 



Whenever RNRX = 1, the l-field of a received frame 
is not brought into memory. For received packets, 
the N(S) and N(R) are checked as usual. If the N(S) is 
out-of-sequence, the REJ will not be transmitted. 

If a link resetting SABM is transmitted when RNRX 
= 1 , RNRX will be cleared when the UA is received. 
If the condition which caused receiver-not-ready still 
exists, an RNR is sent and RNRX is set. However, if 
the receiver instead is ready, l-field data may be 
brought into memory. 

The same also applies when a link resetting SABM 
is received. 



28 



STATE TABLE V 

REMOTE STATION BUSY (RECEIVED RNR: RNRR = 1) 



SEND 


NA AND NB 


RECVD 
ACK? 


RECVD 
RNR 


RECVD RR, 
REJ OR UA 


T1 EXPIRES 


ACTION 


X 


not = 


Yes 


Yes 


No 


No 


Set RNRR. Restart T1 and 
N2. Update NA. 





Equal 


No 


Yes 


No 


No 


Set RNRR. Start T1. 


X 


not = 


No 


No 


No 


Yes 


Send S-command (P = 1). If 
RNR subsequently received 
restart T1 and IM2. 


X 


not = 


Yes 


No 


Yes, but not UA 


No 


Clear RNRR. Restart T1 and 
N2. Update NA. 


X 


X 


X 


No 


Yes 


No 


Clear RNRR. 


0-1 


Equal 


No 


No 


No 


No 


Send next packet. Increment 
NB after transmission. (Then, 
NB does not = NA). Start T1 
and N2. 



o 

oi 



2. NOTES OF TABLE V 

1 . If SEND = 1 , it is assumed for this table that BRDY 
of the next TLOOK segment is set. 

2. If RNRR = 1, an RR or RNR command is transmit- 
ted at T1 intervals. 

SENDING S-FRAME COMMANDS 

When an S-frame command is to be transmitted, an RR 
command is transmitted if RNRX = or an RNR com- 
mand is transmitted if RNRX = 1 . If RNRX = 0, and a 
REJ is waiting to be transmitted, a REJ command is 
transmitted. 

For all transmitted S-commands, the P bit is set to 1 . 

An S-command will be transmitted at T1 intervals if an 
RNR is received (RNRR = 1)or if T1 has expired due to 
waiting for an acknowledgement to previouusly trans- 
mitted packets. 

CONDITIONS FOR SENDING SABM (LINK RESET) 

1. FRMR received. 

2. Have sent an S-command N2 times with P = 1 (at 
T1 intervals) without receiving an S-response with 
F = 1. 

UNSOLICITED UA OR UNSOLICITED F BIT 

If an unsolicited UA or an unsolicited F bit is received 
with the link up, a FRMR will be transmitted with W = 1 . 

SENDING AN FRMR 

An FRMR may be transmitted for any of the reasons 
indicated in X.25 (W, X, Y, Z). An FRMR is transmitted 
only if the link is up. 

Upon sending a FRMR, the WD2511 will not send a 
packet until the FRMR condition is cleared. The 
WD2511 will also discard any received l-fields. The 
FRMR condition is cleared when either a SABM or 
DISC is received. 



If an S or l-f rame is received which acknowledges a pre- 
viously transmitted packet(s), the acknowledgement(s) 
is accepted, the appropriate ACKED bits in TLOOK are 
set, and there is an XBA interrupt. 

While in the FRMR condition, the WD2511 will act as 
shown below: 



FRAME RECEIVED 


ACTION BY WD2511 


SABM 


Send UA. Clear FRMR 
condition. Enter infor- 
mation transfer phase. 


DISC 


Send UA. Clear FRMR 
condition. Enter logical 
disconnect state. 


Packet with good N(R) 


Retransmit FRMR 


S-frame with good N(R) 
(command or response) 


Retransmit FRMR 


Packet or S-frame with 
bad N(R) 


Transmit new FRMR (Z 
= 1) 


Any frame with violation 
W,X,Y 


Transmit new FRMR 



RECEIVING AN FRMR 

After a FRMR has been received: 

1 . The FRMR l-field will bee in the memory referenced 
by the current NE segment, provided the receiver 
was ready. 

2. The SEND bit is cleared. 

3. No more l-field data is allowed to come into memory 
until the user makes the receiver memory ready. 

4. A link resetting SABM is transmitted and an error 
interrupt, ERO = CO is generated. 

5. After the UA is received for the SABM, the NA, NB, 
NE, V(R), and V(S) are cleared to 0. 



29 



o 

01 



PROTOCOL SIGNIFICANCE OF TLOOK/RLOOK 
POINTERS 

The NE, NA, and NB pointers have a relationship with 
the sequence counters used in the LAPB protocol. 

The RLOOK pointer NE is equal to V(R) at all times if 
TRCV = 0. However TRCV = 1 and the link is UP, there 
is no guaranteed relationship between NE and V(R). 

TLOOK pointer NB is the Next Block to be transmitted. 
If the chip is not in packet retransmission, NB is equal 
to the V(S) of the next new packet to be transmitted. 

TLOOK pointer NA is the Next packet to be Acknowl- 
edged. It represents the V(S) number for the oldest 
packet in the retransmission buffer. 

USEOFTHERECRBIT 

The RECR (CR01) bit should be understood as an 
instruction to the WD2511 to enable the receiver func- 
tion. The WD2511 will test RECR as soon as MDISC is 
cleared, and will retest RECR after each link set-up and 
each link reset. Once the receiver is ready, the WD2511 
will not test RECR again unless there is a link set-up or 
a link reset. 

The receiver-not-ready condition is indicated by RNRX 
= 1 . This condition is cleared after the user makes 
RECR = 1 with RECRDY = 1 (in RLOOK #0) and after 
either a packet or an S-frame is received from the 
remote station. 

If RECRDY of the next RLOOK is but RECR = 0, 
there will not be an RLNR interrupt, but RNRX will be 
set. If RECR = 1 but the RECRDY bit of the next 
RLOOK segment is 0, there will be an RLNR interrupt 
(error code 10) and RNRX will be set. 

HOST PROCEDURE FOR LINK RESET 

The host should keep its own set of variables to deter- 
mine the index of the Next Packet to be Received and 
the Next Packet to be Acknowledged because if a Link 
Reset occurs, the chip resets its NA, NB, and NE 
counters. After a Link Reset the host should look for 
unprocessed received packets (FRCML = 1) in the 
RLOOK table beginning at its Next Packet to be 
Received segment and proceeding in order until it finds 



FRCML = 0. Furthermore, if RLOOK0 has RECRDY = 
1 and RECR is set to 1, a packet can be stored into 
RLOOK0 immediately after a Link Reset. Therefore, 
the host should also look for received packets begin- 
ning at RLOOK0 after a Link Reset. 

The chip resets the SEND bit after a Link Reset so no 
new TLOOK buffers will be sent until the host sets 
SEND again. After a Link Reset the host should look for 
any unprocessed acknowledged packets (ACKED = 1) 
in the TLOOK table beginning at its Next Packet to be 
Acknowledged segment and proceeding in order until 
it finds a segment with ACKED = 0. Then the host must 
set up the TLOOK segments again so that the oldest 
unacknowledged packet is in TLOOK0, the next in 
TLOOK1, and so on, setting the BRDY = 1 in each 
occupied segment. (New packets may be added to the 
TLOOK at the next available segment.) When the host 
has finished setting up the TLOOK segments, it should 
set the SEND bit to 1 . At this point packet transmission 
will resume if the remote station is up and is not in a 
receiver not ready (RNRR = 1) condition. 

When presenting packets to the chip for transmission, 
the host should implement a timer. The value of the 
timer is system dependent and varies with packet size 
and line speed but should be in the order of seconds. If 
a packet has not been acknowledged by the time the 
timer expires, the host should check the SEND bit. If it 
is reset, set it to 1 again and restart the timer. If it was 
still set, the link must be reset. Do this by setting the 
MDISC bit (CR00 = 1), waiting for the link to go down 
(LINK = 1), then resetting MDISC (CR00 = 0), and 
waiting for the link to come back up (ER0 = 21 or, if 
RLOOK0 was not ready, 11 and LINK = 0). 

For more software information refer to the WD2511 
Application Note. 



30 



APPENDIX D 

GLOSSARY OF DATA COMMUNICATIONS TERMS 

The following is a list of industry-accepted data communications terms that are applicable to this specification. 

ABM Asynchronous Balanced Mode 

ADCCP Advanced Data Communications Control Procedure (ANSI BSR X3.66) 

ANSI American National Standards Institute 

ARM Asynchronous Response Mode 

CCITT International Consultative Committee for Telegraphy and Telephony 

CMDR Command Reject. A U-Frame 

DCE Data Circuit Termination Equipment (the network side of the DTE/DCE link) 

DISC Disconnect. A U-Frame 

DTE Data Terminal Equipment 

DM Disconnect Mode. A U-Frame (LAPB, only) 

ECMA European Computer Manufacturers Association 

FCS Frame Check Sequence 

FDX Full Duplex (also called "two way simultaneous") 

FRAME Basic serial block of bit-oriented data. Includes leading and trailing flags, address field, control field, 
FCS field, and an optional information field. 

FRMR Frame Reject. A U-Frame (LAPB, only) 

HDLC High-Level Data Link Control (ISO 3309) 

HDX Half Duplex (also called "two way alternate") 

HOST Another name for a DTE 

l-Frame Information Frame. Control field bit is 0. In X.25 an l-frame is a packet. 

ISO International Standards Organization 

LINK The logical and physical connection between two data terminals 

LAP Link Access Procedure 

LAPB Link Access Procedure Balanced 

N2 Maximum number of retransmissions of a frame. (Also called retransmission count variable.) 

NODE Another name for a DCE or DTE. 

N(R) Sequence number of next frame expected to be received. 

N(S) Sequence number of current frame being transmitted. 

OCTET An 8-bit byte 

PACKET An l-Frame in X.25 

PAD Packet Assembly/Disassembly facility 

REJ* Reject. An S-Frame 

RNR* Receiver Not Ready. An S-Frame 

RR* Receiver Ready. An S-Frame 

S-Frame Supervisory Frame. Control field bit = 1 and bit 1 =0 

SARM Set Asynchronous Response Mode. (LAP, only) 

SABM Set Asynchronous Balanced Mode. (LAPB, only) 

SDLC Synchronous Data Link Control (IBM document GA27-3093) 

T1 A Primary Timer for a delay in waiting for a response to a frame 

U-Frame Unnumbered Frame. Control Field bit = 1 and bit 1 =1 

UA Unnumbered Acknowledge. A U-Frame 

X.25 Recommendation by CCITT on Interfacing to Public Packet Switching Networks 



D 
io 



31 



X.3, X.28, X.29 Recommendations by CCITT involving PAD facilities 

*There are also RR, RNR, and REJ packets which are not the same as the S-frame RR, RNR and REJ discussed in 
this document. 



ORDERING INFORMATION 

Order Number Maximum Data Rate 

WD2511AN-01 100 Kbps 



500 Kbps 
1.1 Mbps* 

' Higher speeds available on special order. 



WD2511AN-05 
WD2511AN-11 



Package Diagram 




48 LEAD CERAMIC "T" or "AN" 



32 



WESTERN DIGITAL 

CORPORAT/ON 

Application Note 
Using The WD2511 



This application note provides an introduction to the 
X.25 communication protocol and introduces the ISO 
reference model. The link layer of X.25 is highlighted 
as it can today be implemented with a single LSI 
device, the WD2511. 

The bulk of this document provides details of the hard- 
ware and software interfaces that a user typically 
encounters when using the WD2511. Schematic and 
timing diagrams for a typical Z80 interface along with 
high level flowcharts for initialization and operation are 
given. This circuitry is applicable for applications 
where the TC/RC speed is 64 Kbps and below. 



CONTENTS 

1 .0 The WD2511 General Description 
2.0 The WD2511 and the ISO Model 
3.0 Hardware 
4.0 Software 
Appendix A Glossary 
Appendix B LAPvsLAPB 



1 .0 THE WD2511 GENERAL DESCRIPTION 

The WD2511 is an LSI device that fully handles the link 
level (level 2) of the CCITT X.25 communications 
protocol. 

In addition to the traditional parallel/serial converters 
and FCS logic, the WD2511 incorporates a highly effi- 
cient micro-programmed processor that fully handles 
the required link set-up and frame sequencing opera- 
tions conventionally delegated to a "user defined" 
processor. The WD2511 also contains an intelligent 
two-channel DMA controller to further simplify its inte- 
gration into a user's system. 



2.0 THE WD2511 AND THE ISO MODEL 

The CCITT X.25 recommendation comprises three 
levels of protocols (Level 1 to 3). See Figure 1 . 

Level 1 is the physical level, which concerns the actual 
means of bit transmission across a physical medium. 

Level 2 is the link level which includes frame format- 
ting, error control and link control. 

Level 3 is the packet (network) level which controls the 
traffic of the different virtual calls and multiplexes these 



for passage over the physical line. 

These three levels are completely independent of each 
other, which allows changes to be made to one level 
without disrupting the operation of any other level. An 
adjacent level is affected only if the changes affect the 
interface to that level. 

Each level performs one well defined set of functions, 
using only a well defined set of services provided by the 
level below. These functions implement a set of 
services that can be accessed only from the level 
above. Each level is strictly controlled by the systems 
engineer according to formal functional and interface 
specifications. 

The WD2511 implements level 2. Without additional 
logic, it generates the frame, performs error checking, 
performs link management (set up/disconnect) and 
ensures reliable data transmission by evaluating the 
sequence number associated with each l-frame. The 
device automatically acknowledges received l-frames 
and fully supports up to 7 outstanding (unacknow- 
ledged) frames, including retransmission if required. 



3.0 HARDWARE 

The WD2511 must be connected to the Physical Level 
(Level 1). This generally amounts to simple line drivers/ 
receivers. 

A typical X.25 DTE/DCE station block diagram is 
shown in Figure 2. Figure 3 shows a circuit diagram of 
the actual X.25 hardware interface of this same station. 
Table 1 is a description of signal functions for this circuit 
diagram. This is to be connected directly to a Z80 
microprocessor on one side and an EIA RS-422 inter- 
face on the other side. 

Figures 4 and 5 are DMA cycle timing diagrams for this 
particular station. 

General notes to this interface: 

• A modem would be needed for long-distance com- 
munication lines. 

• The hardware interface in Figure 3 includes all hard- 
ware options. Simpler interfacing is possible. 

• The function of the CPU Bus Driver Control Circuit 
(CBDCC) is to control the direction and/or timing of 
the data-line transceivers and the two address 
latches. 

• If the CPU clock frequency is not higher than the 
WD2511 CLK maximum frequency, the High Speed 
Control Circuit (HSCC) is not needed. The function 
of the HSCC circuit is to divide a high speed CPU 



33 



LEVEL 




«♦ — 





— 






4-7 


USER 
PROCESS 


USER 
PROCESS 




LEVEL 3/4 INTERFACE 


1' 






3 


PACKET 
LEVEL 


PACKET 
LEVEL 












LEVEL 2/3 INTERFACE 








2 


LINK 
LEVEL 


LINK 
LEVEL 






PHYSICAL 
LINK 






LEVEL 1/2 INTERFACE 








1 


PHYSICAL 


PHYSICAL 






LEVEL 








LEVEL 





DTE DTE/DCE 

Figure 1. LAYERED ARCHITECTURE FOR COMPUTER NETWORKS 



The only real physical connection between the two sta- 
tions (DTE and DTE/DCE) is the Physical Link between 
the two physical layers. The other connections shown 
between two of the same layers (peer to peer interface) 
is not a physical but rather a logical connection made 



up by the respective protocols for that particular level. 

Each level n "interfaces" to the corresponding level n 
on the other side of the Data Communication Link 
through the level n-1, then n-2 etc., via the physical link 
and up through the levels to n-2, n-1 and to level n. 



clock signal (0) down t o half the frequency (01 A). It 
also delays the reset of BUSRQ with one additional 
01 clock cycle when a high speed CPU clock is used. 
These functions are needed to e stablis h a time win- 
dow of at least 500ns between DACK being active 
and a CPU Write/Read function. 

When a high speed CP U clock is used, con nect 01 A 
signal to 01 signal and BUSRQA signal to BUSRQ 
signal. When a low speed CPU clock is u sed, con- 
nect CP U clock ( 0) direct to 01 signal and BUSRQ2 
signal to BUSRQ signal. 

The DMA I/O circuit matches the timing between the 
Z80andtheWD2511. 

The RTS open collector output needs a pull-up 
resistor. 

In this particular example, line drivers/receivers are 
of type EIA RS-422. However, RS-232C or RS-423 
can also easily be used. 

Port A of a PIO in this example is programmed to be 
an output. In this case, the CPU controls the DTR 
output to the modem. Port B of the PIO is 



programmed to be interrupt contr olled in puts; the 
CPU can be interrupted by DSR and/or INTR as 
programmed. 



• MRW (Memory Read/Write) signal enables the out- 
put of the memory address decoder for the com- 
puter system memory chips. As an example, if a 
PROM ty pe 28S 42 is used as the memory address 
decoder, MRW is connected direct to E (Pin 15) 
input. 

• The WD2511 CS input is to be connected to a port 
addre ss decoder (or mem ory addres s dec oder). 
MWE is connected to all WE inputs, and MOE is con- 
nected to all OE inputs of the system memory chips. 

• REPLY output is not used in this application. 
3.1 READ/WRITE CONTROL OF I/O REGISTERS 

The sixteen I/O registers are directly accessible from 
the CPU data bus (DAL0-DAL7) by a read and/or write 
operation by the CPU. The CPU must activate the 
WD2511 register address (IA0-IA3). Chip Select (CS). 
Write Enable (WE) or Read Enable (RE) before each 
data bus transfer operation. The read/write operation is 



34 



completed when CS or RE/WE is brought high. During 
a write operation, the falling edge of WE will initiate a 
WD2511 write cycle. The addressed register will then 
be loaded with the content of the Data Bus. The rising 
edge of WE will latch that data into the addressed 
register. 

During a read operation, the falling edge of RE will initi- 
ate a WD2511 read cycle. The addressed register will 
then place its content onto the Data Bus. 

The CPU must set-up all transmit data, TSADR HI and 
LO, TCNT HI and LO, and residual bits before setting 
BRDY in the applicable TLOOK segment. 

The CPU must set aside receiver memory (at least one 
chain segment with transfer address), and set-up 
RSADR HI and LO before setting REC RDY in the appli- 
cable RLOOK segment. 

3.2 DMA IN/OUT OPERATION 

The Direct Memory Access (DMA) operation is com- 
pletely controlled by the WD2511 . During a DMA cycle, 
the CPU sets its address bus, data bus and three-state 
control signals to their high impedance states. 

(See DMA In/Out timing diagrams, Figures 4 and 5.) 

In this application example, the data bus transceivers 
are permanently enabled (low impedance state). When 
the CPU has control, the direction of these transceivers 
is pointing from the CPU bus towards the WD2511 . Dur- 
ing a DMA In cycle, this is not changed. During a DMA 
Out cycle however, the direction is reversed (WD2511 
towards the CPU bus). 

The address bus latches are in high impedance state 
while the CPU has control of the bus. When the 
WD2511 has control of the CPU bus, the address 
latches are in the low impedance state. During the 
DMA Out cycle, these latches function as regular bus 
drivers. During the DMA In cycle however, the address 
gets latched to assure enough data hold time for the 
WD2511 . 

3.2.1 DMA IN 

During a DMA In cycle, the task of transferring one byte 
of l-field data from memory into the WD2511 is per- 
formed. The CPU time (in the example described in this 
paragraph to execute this task) is five T-states for a low 
speed CPU clock system and ten T-states for a high 
speed CPU clock system. 

The DMA In function starts when the WD2511 is ready 
to receive a byte from memory to be transmi tted ou t to 
the remote station. This condition causes the DRQ I sig- 
nal to go LO, which in turn activates the BUSRQ (Bus 
Request) signal. Also at this time (ADRV bit = 1), the 
WD2511 presents the address (on A0-A15) of the data 
byte to be retrieved from memory. 

The BUSRQ signal is sampled by the CPU with the ris- 
ing edge of the last CPU clock (0) p eriod of any 
machine cycle. In this case, because the BUSRQ sig- 
nal is active, the CPU goes into high impedance state 
with the rising edge of the next CPU clock pulse. At this 



time, the CPU also switc hes the control over to the 
WD25 11 by activating the BUSAK signal. This causes 
DACK to go LO at the following rising edge of 01 clock. 
This is the act ual ind ication for th e WD2 511 to start the 
DMA In cycle. DACK also causes DRQI to return to the 
HI state. 



At the next rising edge of the 01 clock, MOE (Memory 
Output Enable) is activated. This causes the memory to 
output the addressed data byte onto the Data Bus. 
Also, the address is now latched into the address bus 
latches (74LS373) at this time. 

At the next falling edge of the 01 clock, DACK gets 
deactivated, causing the WD2511 to latch the data byte 
(DAL0-DAL7) and to set its address lines (A0-A15) to 
logical HI state (ADRV bit = 1). T he add ress bus 
latches hold the address active until DMOE signal is 
deactivated. 

At the n ext risin g edge of the 01 clock (low speed CPU 
clock), BUSRQ gets deactiva ted. When high speed 
CPU clock is used, BUSRQ is deactivated after an 
additional 01 clock cycle. 

At the next following rising edge of 01 clock , B USRQ is 
sampled by the CPU. This causes BUSAK and MOE to 
become deactivated, but not until the next falling edge 
of the CPU (0) clock. This is the end of the DMA In 
cycle. At the next rising edge of the CPU clock, the 
CPU again controls the CPU bus. 



3.2.2 DMA OUT 

This operation is very similar to the DMA In function. 
During this cycle, one byte of l-field data is transferred 
from the WD2511 to the memory. The CPU-time in this 
example described to perform this task is the same as 
for the DMA In cycle. 

The DMA Out function starts when the WD2511 is hold- 
ing a received l-field byte and is ready to transfe r this to 
the memory. This con dition acti vates the DRQO signal, 
which in turn sets the BUSRQ to LO. Also at this time 
(ADRV bit = 1), the WD2511 presents the address to 
the memory location to where the respective data byte 
is to be loaded. 



The BUSRQ signal is sampled by the CPU with the ris- 
ing edge of the l ast CPU clock period of any machine 
cycle. Since the BUSRQ signal is active, the CPU goes 
into high impedance state with the rising edge of the 
following CPU clock pulse. Now the CPU also switches 
the con trol over to the WD2511 by activating the 
BUSAK signal. This causes DACK to go LO at the next 
rising edge of 01 clock, which indicates to the W D2511 
to start the DMA Out cycle. This causes DRQO to reset 
back to HI state and to load the data byte to be transfer- 
red onto the data-bus. 



At the next rising edge of the 01 clock, MWE (Memory 
Write Enable) is activated. This causes the memory to 
input the addressed data byte. 

At the following rising edge of the 01 clock, MWE goes 
HI, latching the data into the memory. Also at this time 



35 



TABLE 1 . SIGNAL NAMES FOR THE HARDWARE INTERFACE (See Note) 



NAME 


SYMBOL 


FUNCTION 


RECEIVE 

DRM TRANSFER 

DMA MEMORY OUTPUT ENABLE 


RCV 


When activated (LO), sets the direction of the data 
bus transceivers from WD2511 towards the CPU 
bus. This is done only during CPU Read or DMA 
Out cycle. 

When activated (LO), enables the output of the 
address bus latches. This is done during a DMA 
In/Out cycle. 

Is activated during a DMA In cycle. Generates the 
MOE signal and latches the DMA In addresses. 


DTFR 


DMOE 


MEMORY OUTPUT ENABLE 


MOE 


Is activated during a DMA In or a CPU Read 
cycle. Enables the memory outputs. Is to be con- 
nected to the OE pin of the memory circuits. 


MEMORY WRITE ENABLE 


MWE 


Is activated during a DMA Out or a CPU Write 
Cycle. Enables the memory write function. Is to 
be connected to the WE input of the memory 
circuits. 


MEMORY READ/WRITE 


MRW 


Is activated during a DMA In/Out function or a 
Memory Read/Write cycle by the CPU. Enables 
the output of the Memory Address decoder. 


DMA OUT 


DMA OUT 


Is activated during a DMA Out function. 


DMA IN 


DMA IN 


Is activated during a DMA In function. 


INTERNAL LOOP 
BUS ACKNOWLEDGE 1 

BUS REQUEST 1 
BUS REQUEST 2 

BUS REQUEST A 


I LOOP 


Is activated during an internal loop-back test. 
Keeps the RTS signal to the modem in off condi- 
tion and logically connects RTS to CTS. 

When active, indicates that the CPU has switched 
bus control over to the WD2511. Compared to 
BUSAK signal, this is delayed one 01 clock cycle 
when going LO to allow a time window of at least 


BUSAK1 


500 ns before DACK becomes activated. 


BUSRQ1 


When active, requests the CPU via BUSRQ2 and 
BUSRQ (low speed CPU clock) to switch control 
overtotheWD2511. 


BUSRQ2 


Same function as BUSRQ1, except that BUSRQ2 
is delayed one 01 cycle when going HI. The delay 
allows a time window of at least 500 ns between 
DACK being active and a CPU Read/Write 
function. 


BUSRQA 


Same function as BUSRQ2, except is delayed an 
additional 01 cycle when going HI. This delay 
allows the necessary 500 ns time window 
between DACK being active and a CPU Read/ 
Write function when an high speed CPU clock is 
used. This is then directly driving the BUSRQ 
signal. 



(low speed CPU clock), BUSRQ signal g ets deac ti- 
vated. When high speed CPU clock is used, BUSRQ is 
deactivated after an additional 01 clock cycle. 

At the next rising edge of 01 clock, the BUSRQ signal is 
sampled by the CPU. 

DACK goes HI half a 01 clock cycle after MWE goes HI. 
This ends the DMA Out cycle by the WD2511 setting its 



data-lines in high impedance state and the address- 
lines (A0-A15) to logical HI state (ADRV bit = 1). 

After CPU has sampl ed and detected BUSRQ being 
deactivated, it resets BUSAK to HI at the next falling 
edge of the CPU clock. 

At the next rising edge of the CPU clock, the CPU again 
controls the bus. 



36 



TABLE 1 . (Continued) SIGNAL NAMES FOR THE HARDWARE INTERFACE (See Note) 



NAME 


SYMBOL 


FUNCTION 


01 

01 A 

+ 5 RESISTIVE 


01 

01 A 
+ 5R 


Clock used for timing of this hardware interface. 
The 01 frequency is not allowed to be higher than 
the CLK maximum frequency of the WD2511. 
When a low speed CPU clock is used, 01 signal is 
connected directly to the CPU clock (0). When a 
high speed CPU clock is used, this is connected 
to the 01 A signal. 

Clock signal with half the CPU clock frequency. 
This is driving the 01 clock when a high speed 
CPU clock is used. 

+ 5V through a resistor. 



NOTE: Signals described in this paragraph are signals generated by this circuitry only. Other signals are described 
in either the WD2511 device specification or in the Z80 CPU data sheets. 



COMPUTER 






COMPUTER 
INTERFACE 




WD2511 






LINE 

DRIVERS 

RECEIVERS 






MODEM 






TO/FROM 
REMOTE 
STATION 




V 






J 






























V 
FIGURE 3 











FIGURE 2. DTE/DCE STATION BLOCK DIAGRAM 



37 



EIA RS-422 LINE DRIVERS/RECEIVERS 



r 



m 

3J 

I 

m 



GND RCV 


DRQO - 








+ 5V 








| | 


DRQ1 
DRQO 
J?ALO 


RTS 

TD 

CTS 
RD 
RC 

TC 

1/ 

v cc 
v S s 

CLK 

V DD 


h 


B + 

B|N £b- 
din d + 

EM D " 






'do 


CE SR 

AO BO 

74 LS 
245 

A7 S7 








D1 




DTR 
MC — . 






D2 












D3 








D4 




— NC 




D5 






D6 
















D7 




DAL7 
TAO 

I 

TA3 
AO 


I GND 






















A- 

B £ 8 + 

> B- 

C £ C + 
C- 

D ° + 
EM D " 


100Q (5ML) 




A1 






A2 








A3 


^^-1 




DMOE 




-DTFR 
AO 








AO * 


E OE 

QO DO 

74 LS 

373 

07 D7 


«-w-, 












A1 


A1 








WD250 
2511 


U*-, 




A2 


A2 










A3 


A3 




l^GND 




A4 


A4 


TO Z80 J 


A5 


A5 


DSR 

MC 

MC 

MC 


g 8- 

S C + 
c ^C- 
D + 
D 

EM D- 




CPU BUS 


A6 


A6 


Lvv-i 




A7 


A7 


A7 
A8 


* 




DMOE- 




— DTFR" 
A8 






A8 


E OE 
QO DO 

74LS 
373 

Q7 D7 


MC 




A9 


A9 


M_ 




A10 


A10 










A11 


A11 


MC 




A12 


A12 


+5V 


*-C 


ND 




A13 


A13 






A14 


A14 






A15 


A15 


A15 

WE 

MTR 
CS 














WR 


WR 






RD RD 


01 




RESET 


(<2 MHz) 






4S-SDKR 

MRB ° MFIEg MC 


DACK 






INTR 






C3~ 


t U 












R 







( WE 

I -— f MWE 

' \ MOE 



FROM CS 

PORT ADDRESS ^— CS 
DECODER 





Sx*- 



... 



HSCC 



+6R _r 



+ 5R I 



NOTE: 

Connect to 01 and BUSRQ2 to BUSRQ if following conditions are 
true: 

1 . WD2511 CLK max. frequency > CPU frequency. 

2. CPU frequency< 2.0 MHz 

If above conditions are not true, connect 01 A to 01 and BUSRQA to 
BUSRQ. 



ANY M 
CYCLE ' 



k 



CPUO 
(NOTE 1) 



\.f 



I 1 i 1 r 

J l-_j L.J 



DMA IN CYCLE 
L_J" ' 



I ANY M 
r+- CYCLE 



L.J- 



-i r - 1 r 
i ■ i i 



l_-J i J L_J 



01 
(NOTE 1) 



BUSRQ 



"L 



j — i r 



T DD 



(NOTE 1) 



"l_ 



J ! (NOTE 1) 



DACK 



A0-A15 
(WD2511) 



DAL0-DAL7 
(WD2511) 



~H H"~ T DA1 



T DAO 



"*1 I*" 



T DAH 



| (NOTE 3) 



~H [*— MEMORY OUTPUT 
—l ENABLE ACCESS TIME 



NOTE: I 

1 . These dashed lines show the respective signals when a fast 
CPU clock is used. Solid lines show same signals for a 
slow CPU clock (CPU = 01). 

2. Propagation delay is omitted in this diagram unless timing 
symbol is shown. 

3. Data would become non-valid after the address becomes 
non-valid if address latches were not used. 



J ) (NOTE1) 



Figured DMA IN TIMING 



CPU 
(NOTE 1) 



ANYM 
CYCLE 



I 



._J 



L_-f""' 



DMA OUT CYCLE 



J""" 



1 I i 

I I ■__. 



- i — -j r-i i — T i — 1 



■ i ■ 



ANY M 
1 CYCLE 



01 
(NOTE 1) 



1_ 



DRQO 



BUSRQ 



TDD 



(NOTE 1) 



L I (NOTE 1) 



A0-A15 
(WD2511) 



T DAO 



-Hl-T 



DAL0-DAL7 
MWE - 



T DA1 



TRD"H 



NOTE: I 

1 . These dashed lines show the respective signals when a fast 
CPU clock is used. Solid lines show same signals for a 
slow CPUO clock (CPUO = 01). 

2. Propagation delay is omitted in this diagram unless timing 
symbol is shown. 



(-•— Tdah 



> 



T DMW 



Figure 5. DMA OUT TIMING 



39 



3.3 SERIAL INTERFACE 

The receiver and transmitter sub-systems are com- 
pletely independent of each other, the CPU Read/Write 
functions and the DMA In/Out functions. 

The serial data is synchronized by the externally sup- 
plied TC clock and RC clock. The falling edge of TC" 
generates new transmitted data and the rising edge of 
RC is used to sample the received data. 

After initilization and before the first frame is sent, the 
TD output sends Idles (continuous 1s). 

After the first frame is sent or the ACTIVE/PASSIVE bit 
is set, continuous flags are sent in between frames. 

For detailed information on what type of frames are 
sent for certain conditions, see the WD2511 specifica- 
tions. 

4.0 SOFTWARE 

Initialization of the WD2511 and l-field data processing 
(level 3) is accomplished by user written software. This 
software need not be realtime, since the WD2511 
responds to link exceptions and overhead functions on 
its own. 

Configuring the WD2511 for certain test functions, 
modes, timer values, location of initial memory 
pointers, chain buffer lengths and link level addresses 
is performed via the sixteen I/O registers. 

All buffer management support, buffer chaining and 
free/busy flags occur in user memory. Here two look-up 
tables (TLOOK/RLOOK), located in the user memory, 



contain pointers/counters for up to eight outstanding 
transmit/receive packets. The WD2511 contains only 
one address pointer which is the starting address of 
Segment #0 in the TLOOK table. Segment #0 in the 
RLOOK table always begins 40(Hex) bytes after 
TLOOK, Segment #0, byte #0. See section "Memory 
Access Scheme" in the WD2511 specifications. 

Link monitoring is done by use of the I/O registers and 
the memory buffers. The WD2511 indicates to the sys- 
tem CPU that a certain event has occurred by setting a 
bit in status register 1 and setting the interrupt flag. 
This indicates whether a packet has been received, a 
transmitted packet has been acknowledged, a non- 
recoverable error condition or some other condition 
needs the attention of the CPU. 

In this section a flow-chart is given to show the user how 
to program the WD2511. For more details refer to the 
data sheets. 

The flow for programming/monitoring the WD2511 for 
transmitting or receiving a packet(s) or for a loop-back 
test is shown in the flowchart below. The flow starts at 
START1 if a power-up was just done and/or if no data 
communication environment programming (initializa- 
tion) has been done. 

If initialization is complete, the flow starts at START2 
when the WD2511 is to be enabled to receive a 
packet(s). 

If a packet is to be transmitted and initialization is com- 
plete, the flow starts at START3. 



40 



WD2511 PROGRAMMING FLOWCHART 



INITIALIZATION 



c 



J 



MR MOMENTARILY 3> 10MS 



RESET WD2511 



PROGRAM THE 

WD2511 
FOR THE USER'S 
ENVIRONMENT 



PROGRAM I/O 

REG. 1, 8, 9, 

A AND B. 



XMIT 
COMMAND/ 
RESPONSE 
ADDRESS 




(DTE) 



SET REG. E 
SET REG. F 



SEE PARA- 
GRAPH 
"INTERNAL 
LOOP-BACK 
TEST- 



SET RTS OFF TO 

MODEM. 

ENABLE CTS 

INPUT 



(DCE) 



SET REG. E = 03 
SET REG. F = 01 



RESET RECEIVE 
DATA BUFFERS 



SET 
REG. E = REG. F 



6 



41 



ENABLE RECEPTION 
OF PACKET(S) 




RLOOK 



SET CONTROL 
BITS 



PROGRAM THE 
LOOK-UP TABLES 
FOR THE RECEIVE 

DATA BUFFERS 



SET ACTIVE AND 
RECR BIT 



COMPUTER DOING 
OTHER TASKS 



c 



REC RDYAND 
RSADR 




D 



42 



START 

TRANSMITTING PACKET(S) 

(DATA IS ALREADY LOCATED 

IN THE TRANSMIT DATA 

BUFFER(S)) 




LOAD DATA INTO 
THE TRANSMIT 
DATA BUFFERS 



PROGRAM THE 

LOOK-UP TABLES 

FOR THE TRANSMIT 

DATA BUFFERS 



BRDY, TSADR AND 
TCNT 






' 


' 


SET CONTROL 
BITS 


SET SEND BIT 




1 


' 


COMPUTER 

DOING OTHER 

TASKS 


C wait ) 



SET ACTIVE, 

LOOP-TEST AND 

RECR BIT 



43 



CHAINING TRANSMIT 
DATA SEGMENTS 



CHAIN 



o 



PROGRAM THE 

AMOUNT OF CHAIN 

SEGMENTS 

(REG. C, UPPER 4 BITS) 



LIMIT 



REG.C = YZ(HEX) 
Y = NUMBER OF CHAIN 
SEGMENTS MINUS ONE 



PROGRAM THE 

CHAIN-BUFFER 

SIZE 

(REG. C, LOWER 4 BITS) 



REG.C = YZ(HEX) 
BUFFER SIZE = Z. 
64 x (1 + Z) BYTES 




SET ALL THE 
TRANSMIT XFR 
ADR POINTERS 



6 



44 



INTERRUPT 



READ 
STATUS 




YES 



THE PACKET HAS BEEN RECEIVED 

ERROR-FREE AND IN CORRECT 

SEQUENCE. THE l-FIELD 

DATA HAS BEEN PLACED IN 

THE USER'S MEMORY 



YES 



READ ERROR- 
REGISTER 
(REG. 5) 



c 



D 




A PREVIOUSLY TRANSMITTED 

BLOCK(S) HAS BEEN 

ACKNOWLEDGED BY THE 

REMOTE STATION 




ESTABLISH BY 
CODING THE ERROR- 
REGISTER (REG. 5), IF 
ANY ACTION IS NEEDED 



CHAINING 
RECEIVE | 7 
DATA 
SEGMENTS 



c 




3 



45 



CHAINING RECEIVE 
DATA SEGMENTS 



SET RECEIVE 

XFR ADR POINTER 

IN SEGMENT #0 




READ REG. 6 TO 

ESTABLISH WHICH 

CHAIN SEGMENT IS 

CURRENTLY 

BEING LOADED 



LOAD XFR ADR 

POINTER INTO 

CURRENT SEGMENT 



(COMPUTER DOING 
OTHER TASK) 



c 



J 



46 



CHECK RESULT OF 

LOOP-BACK TEST 

(DATA TRANSFER COMPLETED) 



CHECK 
I/O REGISTERS 



VERIFY CORRECT 

INDICATIONS OF 

THE I/O REGISTERS 



REG. 1 = 00/10 

REG. 2 = NN (UPPER 4 

BITS = LOWER 4 BITS) 

REG. 3/BITS 3-1 = REG.2/BIT3-1 



CHECK 
TLOOK SEGMENTS 



VERIFY TRANSMITTER 

LOOK-UP TABLES 

ARE CORRECT 



CHECK 
RLOOK SEGMENTS 



ACK'ED = 1 
BRDY = 



VERIFY RECEIVER 

LOOK-UP TABLES 

ARE CORRECT 



FRCML = 1 
REC RDY = 
RCNT = TCNT 



VERIFY CORRECT 
DATA 



VERIFY RECEIVED 
DATA IS CORRECT 



CONTENT OF TRANSMIT 

DATA BUFFERS = 

CONTENT OF RECEIVE 

DATA BUFFERS 



( END ) 



47 



4.1 INTERNAL LOOP-BACK TEST (Example 1) 

The loop-back test feature is an internal programmable 
loop-back of data, enabling the user to make an almost 
complete test of the WD2511 . It allows diagnostic test- 
ing of the WD2511 and the interfacing circuitry. In this 
mode, transmitted data to the TD pin is internally routed 
to the received data input circuitry, thus allowing this 
WD2511 to set-up a link, send a number of packets to 
itself and then reset the link. 

The RC clock is internally connected to TC clock. CTS 
input however, must be connected externally to GND or 
the RTS output. 

The loop-back test allows the verifying of proper opera- 
tion of practically all the various functions of the 
WD2511 . The features tested here, the addresses and 
values of the variables chosen are only used as exam- 
ples and are as follows: 

TLOOK segments starting address = 0800H 
Transmit Data buffer #0 starting address = 1000H 
Received Data buffer #0 starting address = 1800H 
Number of packets transferred = 1 
Number of l-field bytes per packet = 1024 
Number of residual bits = 
T1 = 101 H 
N2 = 20H 



Chaining is used in this example. The 1024 bytes are 
divided into 256 byte chain segments. Five segments 
are needed for this operation with 256 bytes of l-field 
data and two XFR ADR bytes per segment in the first 
four chain-segments. The rest of the l-field data (8 
bytes) are located in the fifth chain-segment. 

Programming: 

CHAIN = 4 = number of CHAIN segments -1 
LIMIT = 3 = (number of bytes per segment divided by 
64) -1 

For buffer management programming, see memory 
access scheme in Figure 7. 

XMIT Command Address and XMIT Response 
Address (REG. E and F) must be the same value. 

In some applications it is necessary to keep the RTS 
signal to the modem in the Off condition during internal 
loop- back test. Also, to accomplish the mos t com plete 
test, RTS output should be connected to CTS input 
externally (not done internally). Figure 6 shows one 
example of how to implement these two functions. The 
ILOOP signal is connected directly to a PIO output. 

In the loop-back test example shown in this section, the 
logic in Figure 6 is used and contains the Z80 CPU, pro- 
grammable I/O (PIO) etc., as shown in Figure 3. 




PIO/A1 ILOOP 



RECEIVER 



Figure 6. LOGIC FOR INTERNAL LOOP-BACK TEST 



48 



TRANSMITTER 
CHAIN- 
SEGMENT 



TLOOK 0800 







1 




2 




3 




4 




5 




6 




7 


RLOOK 0840 







1 




2 




3 




4 




5 




6 




7 


0880 


ERROR 
COUNTERS 




DATA BUFFERS 



DATA 




Figure 7. MEMORY ACCESS SCHEME FOR LOOP-BACK TEST 
(Example 1) 



49 



APPENDIX A 

GLOSSARY OF DATA COMMUNICATIONS TERMS 

The following is a list of industry-accepted data communications terms that are applicable to this specification. 

ABM Asynchronous Balanced Mode 

ADCCP Advanced Data Communications Control Procedure (ANSI BSR X3.66) 

ANSI American National Standards Institute 

ARM Asynchronous Response Mode 

CCITT International Consultative Committee for Telegraphy and Telephony 

CMDR Command Reject. A U-Frame 

DCE Data Circuit Termination Equipment (the network side of the DTE/DCE link) 

DISC Disconnect. A U-Frame 

DTE Data Terminal Equipment 

DM Disconnect Mode. A U-Frame (LAPB, only) 

ECMA European Computer Manufacturers Association 

FCS Frame Check Sequence 

FDX Full Duplex (also called "two way simultaneous") 

FRAME Basic serial block of bit-oriented data. Includes leading and trailing flags, address field, control field, 
FCS field, and an optional information field. 

FRMR Frame Reject. A U-Frame (LAPB, only) 

HDLC High-Level Data Link Control (ISO 3309) 

HDX Half Duplex (also called "two way alternate") 

HOST Another name for a DTE 

l-Frame Information Frame. Control field bit is 0. In X.25 an l-frame is a packet. 

ISO International Standards Organization 

LINK The logical and physical connection between two data terminals 

LAP Link Access Procedure 

LAPB Link Access Procedure Balanced 

N2 Maximum number of retransmissions of a frame. (Also called retransmission count variable.) 

NODE Another name for a DCE or DTE. 

N(R) Sequence number of next frame expected to be received. 

N(S) Sequence number of current frame being transmitted. 

OCTET An 8-bit byte 

PACKET An l-Frame in X.25 

PAD Packet Assembly/Disassembly facility 

REJ* Reject. An S-Frame 

RNR* Receiver Not Ready. An S-Frame 

RR* Receiver Ready. An S-Frame 

S-Frame Supervisory Frame. Control field bit = 1 and bit 1 =0 

SARM Set Asynchronous Response Mode. (LAP, only) 

SABM Set Asynchronous Balanced Mode. (LAPB, only) 

SDLC Synchronous Data Link Control (IBM document GA27-3093) 

T1 A Primary Timer for a delay in waiting for a response to a frame 

U-Frame Unnumbered Frame. Control Field bit = 1 and bit 1 =1 

UA Unnumbered Acknowledge. A U-Frame 

X.25 Recommendation by CCITT on Interfacing to Public Packet Switching Networks 

X.3, X.28, X.29 Recommendations by CCITT involving PAD facilities 

*There are also RR, RNR, and REJ packets which are not the same as the S-frame RR, RNR and REJ discussed in this document. 



50 



APPENDIX B 

THE DIFFERENCE BETWEEN LAP AND LAPB 

In March 1976, the CCITT adopted Recommendation 
X.25 as an interface standard for public packet-switch- 
ing networks. The link level procedure adopted was 
called Link Access Procedure (LAP) and used the 
HDLC Asynchronous Response Mode (ARM). How- 
ever, ARM was not designed for peer-to-peer communi- 
cations so LAP had some subtle problems. Therefore, 
in 1977, when Provisional Recommendation X.25 was 
adopted, a procedure called LAPB was added. LAPB is 
Link Access Procedure-Balanced and operates under 



the HDLC Asynchronous Balanced Mode (ABM). 
Unfortunately, the 1977 LAPB lacked good symmetry 
between the DTE and DCE, and was unworkable. 

In the April 1979 CCITT meeting, the LAPB was greatly 
enhanced, especially in the DTE/DCE symmetry. This 
enhanced version was approved in the February 1980 
Plenary meeting of the CCITT. We now have a good, 
workable LAPB standard. LAPB is a superior proce- 
dure and the usage of LAP is being replaced with 
LAPB. 



LAPB COMMANDS AND RESPONSES 









CONTROL FIELD 




FRAME TYPE 


COMMAND 


RESPONSE 


BIT# 




l-FRAME 


l-FRAME 




7 6 5 


4 


3 2 1 







N(R) 


P 


N(S) 







S-FRAME 


RR 


RR 


N(R) 


P/F 


1 


RECEIVER 
READY 


RNR 


RNR 


N(R) 


P/F 


10 1 


RECEIVER 

NOT 

READY 


REJ 


REJ 


N(R) 


P/F 


10 1 


REJECT 


U-FRAME 


SABM 




1 


P 


111 1 


SET ASYN- 
CHRONOUS 
BALANCED 
MODE 


DISC 




1 


P 


1 1 


DISCONNECT 




DM 





F 


111 1 


DISCONNECT 
MODE 




UA 


1 1 


F 


1 1 


UNNUMBERED 
ACKNOWL- 
EDGE 




FRMR 


1 


F 


11 1 


FRAME 
REJECT 



Only the FRMR and l-frame contain l-fields 
P = Pole Bit F = Final Bit 



51 



52 



WESTERN DIGITAL 

CORPORATION 



WD2840 Local Network Token Access Controller 



FEATURES 

• Broadcast Medium Independent (Coax, RF, CATV, 
IR, etc.) 

• Up to 254 nodes 

• Dual DMA/Highly efficient Memory Block 
Chaining 

• Token based protocol 

• Acknowledge option on each datagram 

• Adjustable fairness, stations may be prioritized 

• Frame format similar to industry standard HDLC 

• Supports Global Addressing 

• Diagnostic Support: Self-Tests, System and 
Network 

• TTL Compatible 




DESCRIPTION 

The WD2840 is a MOS/LSI device intended for local 
network applications, where reliable data communica- 
tions over a shared medium is required. The device 
uses a buffer chaining scheme to allow efficient mem- 
ory utilization. This scheme minimizes the host CPU 
time requirements for handling packets of data. The 
WD2840 frees the host CPU from extensive overhead 
by performing network initialization, addressing, coor- 
dination, data transmission, acknowledgements and 
diagnostics. 



APPLICATIONS 

The WD2840 is a general purpose Local Network 
Token Controller applicable to virtually all types of 













a 

IO 
00 

o 


DNC 


LZ 




^ 48 


Z3 V CC ( + 5V) 


SQ LZ 


2 


47 


ZDIA1 




WE 


LZ 


3 


46 


Z3 iao 




"cs EZ 


4 


45 


ID IA2 




RE 


LZ 


5 


44 


ZD IA3 




CLK 


LZ 


6 


43 


ZHIntr 




MR 


LZ 




42 


ZDv DD (+i2V) 




DALO 


LZ 


8 


41 


Z3 A5 




DAL1 


LZ 


9 


40 


ZD A4 




DAL2 


LZ 


10 


39 


ZD A3 




DAL3 


LZ 


11 


38 


IZl A2 




DAL4 


LZ 


12 


37 


Z3 A15 




DAL5 


LZ 


13 


36 


ZDA14 




DAL6 


nz 


14 


35 


Z3A13 




DAL7 


LZ 


15 


34 


Z3ai2 




RD 


LZ 


16 


33 


ZJaii 




RC 


LZ 


17 


32 


ZDaio 




(GND)V SS 
TC 


LZ 
LZ 


18 
19 


31 
30 


ZDA9 
ZDA8 




TD 


LZ 


20 


29 


ZDA7 




RTS 


LZ 


21 


28 


IA6 




cts 


LZ 


22 


27 


lAQ 




DRQO 


CZ 


23 


26 


Z]ai 




DRQi 


cz 


24 


25 


IDACK 






PIN DESIGNATION 





multi-point communications applications. The token 
protocol allows the sharing of one bus by up to 254 
nodes. WD2840's will be designed into process control 
equipment, micro-computers, mini-computers, per- 
sonal computers, proprietary micro-processor based 
applications, intelligent terminals, front-end proces- 
sors, and similar equipment. 

The great advantage for the design engineer is the 
ease with which he can implement a local network 
function. The WD2840 handles autonomously all major 
communications tasks as they relate to the local net- 
work function. 



53 



1.1 PIN DEFINITIONS 



PIN NUMBER 


SYMBOL 


PIN NAME 


FUNCTION 


1 


DNC 


DO NOT CONNECT 


Leave pin open. 


2 


SQ 


SIGNAL QUALITY 


An active low input which signals the WD2840 
that a frame may be received. The modem may 
negate this signal if its receive signal quality is 
below a reliability threshold, ensuring that the 
WD2840 will not accept the frame. 


3 


WE 


WRITE ENABLE 


The data on the DAL are written into the 
selected register when CS and WE are low. RE 
and WE must not be low at the same time. 


4 


CS 


CHIP SELECT 


Active low chip select for CPU control of I/O 
registers. 


5 


RE 


READ ENABLE 


The content qfjhe selected register is placed 
on DAL when CS and RE are low. 


6 


CLK 


CLOCK 


Clock input used for internal timing. 


7 


MR 


MASTER RESET 


Initialize on active low. All registers reset to zero, 
except control bit ISOL is set to 1 . DACK must be 
stable high before MR goes high. Status Register 
is not defined at power-up (this register will be 
set-up upon entry into the Network mode). 


8-15 


DALO-7 


DATA ACCESS LINES 


An 8-bit bi-directional three-state bus for CPU 
and DMA controlled data transfers. 


16 


RD 


RECEIVE DATA 


Receive serial data input. 


17 


RC 


RECEIVE CLOCK 


This is a 1X clock input, and RD is sampled on 
the rising edge of RC. 


18 


vss 


GROUND 


Ground. 


19 


TC 


TRANSMIT CLOCK 


A 1X clock input. TD changes on the falling 
edge of TC. 


20 


TD 


TRANSMIT DATA 


Transmitted serial data output. 


21 


RTS 


REQUEST-TO-SEN D 


An open collector output which goes low when 
the WD2840 is ready to transmit either data or 
flags. 


22 
23 


CTS 


CLEAR-TO-SEND 
DMA REQUEST OUT 


An active low input which signals the WD2840 
that transmission may begin. 

An active low output signal to initiate CPU bus 
request so that the WD2840 can output onto the 
bus. 


DRQO 


24 
25 


DRQI 


DMA REQUEST IN 
DMA ACKNOWLEDGE 


An active low output signal to initiate CPU bus 
requests so that data may be input to the 
WD2840. 

An active low input from the CPU in response to 
DRQO_or DRQI. DACK must not be low if CS 
and RE are low or if CS and WE are low. 


DACK 


26-41 


A0-A15* 


ADDRESS LINES OUT 


Sixteen address outputs from the WD2840 for 
DMA operation. 


42 


vdd 


POWER SUPPLY 


+ 12VDC power supply input. 


43 


INTR 


INTERRUPT REQUEST 


An active low interrupt service request output. 
Returns high when Interrupt Register is read. 


44-47 


IA0-IA3* 


ADDRESS LINES IN 


Four address inputs to the WD2840 for CPU 
controlled read/write operations with registers 
in the WD2840. If ADRV = 0, these may be tied 
toA0-A3. 

+ 5VDC power supply input. 


48 


vcc 


POWER SUPPLY 



54 



WD2840 LOCAL NETWORK 
TOKEN ACCESS CONTROLLER 

INTRODUCTION 

The WD2840 is a single LSI device which gives 
systems designers the ability to include networking 
capabilities into their unique products simply and 
economically. 

A general and fundamental advantage to the use of 
complex LSI in a given system is the partitioning of 
required technical expertise. A successful user of the 
WD2840 need not be a data-communications expert, 
and further, he need not be at all concerned with low 
level network details (though these details are docu- 
mented and available to him if he is interested). The 
potential user of the WD2840 must simply evaluate 
the communications facilities provided by the device 
to determine its suitability for the intended use. 



The WD2840 is designed to logically interconnect 2 
to 254 user devices over a shared communications 
medium. Examples of typical mediums include coax 
cable, twisted pair bus, RF, and CATV. All network con- 
trol functions, such as data framing and error checking, 
destination filtering, fair and adjustable transmission 
scheduling, and network initialization and fault recov- 
ery (caused by noise for example) are handled com- 
pletely by the WD2840. 

The protocol implemented allows guaranteed station 
access intervals allowing applications in factory 
automation and other critical communications en- 
vironments where "statistical delays" are not ac- 
ceptable. The WD2840 token protocol also allows the 
addition and/or removal of stations to a network at 
anytime, including while operating. 



a 

00 

© 

















1 


j DALO-7, IAO-3 




REGISTER 

FILE 
(16 HOST 
VISABLE) 


■# *> 


(iT 


ROM 


1 


* 1 / 








k 




»- 


1 






| ALU 


■♦ 


■Iacc 


f 


| 




ROM 


MICROCONTROLLER 




THR, TR 

P/S CONVERTER 

CRC, FLAG GEN 

CONTROL 


« TC 


IWE 








RE 










RTS 




' ' 






i 






cs w . 


' 


I 


I 






_CTS 




CONTROL 




_^__ 


TA 






- INTR 












1 


MR^ 








TD 
















CLK 






^ 




nR 


ROM 




iAO-15 


















- DRQI 


DMA 












1 


i 
















i^RC 


^DRQO 




FIFO 


« 


RR-RHR 

S/P CONVERTER 

CRC FLAG DETECT 

CONTROL 


DACK 


_RD 








^ — 




DMA REGS 
(2 CHAN) 


SQ 












1 


l_ _ 












1 

i 

. 1 



Figure 1 . 1 BLOCK DIAGRAM 



55 



a 

oo 
o 



Serious attention has also been given to the user's 
interface to the device. The interface is a com- 
bination of conventional I/O registers and an 
elaborate DMA buffer chaining interface. This 
chaining feature allows the user much more efficient 
use of his system memory, particularly in situations 
where the maximum message sent over the network 
is much longer than the average size. This feature 
also allows the automatic queueing of messages 
independently of the user's consumption rate, in 
effect, speed decoupling the user's CPU and 
processing requirements from the network. 

The WD2840 has several parameters (registers) that 
allow tailoring to the user's requirements. In this way, 
network priority and access ordering, to name two, 
can be manually set if desired. 

Using an integrated version of these network 
algorithms saves not only the development costs 
already mentioned, but further, the total processing 
power required for the user's application is not in- 
creased. In other words, a CPU upgrade can likely be 
avoided by "distributing" the network processing 
task into LSI devices such as the WD2840. 

SCOPE 

This document differs from traditional LSI data 
sheets in that it details not only the LSI implementa- 
tion of a function, but also defines the overall func- 
tion in detail. Specifically, this document includes de- 



tails of the communications protocol implemented 
by the WD2840 Token Access Controller. 

The document is organized into three main sections: 

SECTION ONE is much like a traditional data sheet 
including register descriptions, pin definitions, and 
hardware architecture. 

SECTION TWO describes the interfaces to the 
WD2840. The network side is conventional, the host 
side consists of an elaborate DMA interface with 
control blocks and WD2840/host handshaking. 

SECTION THREE details the network protocol im- 
plemented by the device. Normal operation, initializa- 
tion, and the handling of error conditions are 
described. 







CPU BUS 








MEDIUM 




CPU 


o 


AO-15 


WD2840 


TD 


MODEM 


l 
■* ► 








DRQl 


« TC 




DRQO 


RTS 






DACK 


^ cTs 




MEMORY 


DALO-7 


« RD 




CS 


< m 








WE 


« SQ 


RE 








IAO-3 










ETC 


, 


INTR 


MR 








* 


TYPICAL SY 


i 
CLK 


k 








'STEM 


CONNI 


ECTION 









56 



1.2 DEVICE ARCHITECTURE 

A detailed block diagram of the WD2840 is shown in 
Figure 1.1. 

Mode control and monitor of status by the user's 
CPU is performed through the Read/Write Control 
circuit, which reads from or writes into registers 
addressed by IA0-IA3. 

Transmit and receive data are accessed through DMA 
control. Serial data is generated and received by the 
bit-oriented controllers. 

Internal control of the WD2840 is by means of three 
internal micro-controllers; one for transmit, one for 
receive, and one for overall control. 

Parallel transmit data is entered into the Transmitter 
Holding Register (THR), and then presented to the 
Transmitter Register (TR) which converts the data to a 
serial bit stream. The Frame Check Sequence (FCS) 
is computed in the sixteen bit CRC register, and the 
results become the transmitted FCS. 

Parallel receive data enters the Receiver Holding 
Register (RHR) from the 24 bit serial Receive Register 
(RR). The 24-bit length of RR prevents received FCS 
data from entering the RHR. The receiver CRC 
register is used to test the validity of the received 
FCS. A three level FIFO is included in the receiver. 

The WD2840 sends all information, network control 
and user data, in blocks called frames. Each frame 
starts and ends with a single flag (binary pattern 
01111110). In between flags, data transparency is 
provided by the insertion of a zero bit after all 
sequences of five contiguous one bits. The receiver 
will strip the inserted zero bits. (See section on frame 
format for location of address, control, and FCS 
fields.) 

1.3 REGISTER DEFINITION 

The WD2840 is controlled and monitored by sixteen 8 
bit registers. This set of registers consists of two 
Control Registers, three Status Registers, an In- 



terrupt Event Register, a Counter Register and a 
variety of Parameter Registers. In general the host is 
responsible for defining these registers (except cer- 
tain host read-only registers: SR0-2, IRO, CTRO and 
NA) to contain proper and meaningful values prior to 
entering Network Mode from Isolate State. Further- 
more, while the WD2840 is in Network Mode, the 
CBP (H,L) and MA registers must not be changed by 
the host. Register NAR may be changed arbitrarily 
but will only be considered by the WD2840 in 
response to the NEWNA (CR10) control bit being set. 
The two Control Registers and the TA, TD, AHOLT, 
TXLT registers may change dynamically to control 
the behavior of the WD2840. 



REG 






[1] 


NAME 


DESCRIPTION 





CRO 


Control Register 


1 


CR1 


Control Register 1 


2[2] 


SRO 


Status Register 


3[2] 


IRO 


Interrupt Event Register 


4[2] 


SR1 


Status Register 1 


5[2] 


SR2 


Status Register 2 


6[2] 


CTRO 


Counter Register 


7[2] 


NA 


Next Address 


8 


TA 


ACK Timer 


9 


TD 


Net Dead Timer 


A 


CBPH 


Control Block Pointer 
(MSB) 


B 


CBPL 


Control Block Pointer (LSB) 


C 


NAR 


Next Address, Request 


D 


AHOLT 


Access Hold-off Limit 


E 


TXLT 


Transmit Limit 


F 


MA 


My Address 



[1] = Hexadecimal representation of IA0-IA3. 
[2] = CPU read only, write not possible. 

Control, status, and interrupt bits will be referred to 
as CR, SR, or IR, respectively, along with two digits. 
For example, SR21 refers to status register #2 and bit 
1, which is "STATE." 



a 
ro 
oo 

o 



57 



oo 



SUMMARY — CONTROL, STATUS, INTERRUPT REGISTERS 


REGISTER 


7 


6 


5 


BIT# 
4 


3 


2 


1 





CRO 


TXDEN 


TXEN 


RXEN 


ITOKON 


I LOOP 


COPY 


NOINT 


ISOL[1] 


CR1[2] 
CR1[4] 


DIAGC 
DIAGC 


PIGT 



INIT 



ADRV 
ADRV 


GIRING 
DMAT 



LOOPT 


TOFF 
RAMT 


NEWNA 
NUDIAG 


SRO 


LASTF 


SENDACK 


L2 





BSZ3 . 


. BSZ2 . 


. BSZ1 . 


. BSZO 


IR0[3] 


ITERR 


IROR 


INS 


ITRAN 


IREC 


ITOK 


ITA 


ITD/M 


SR1 


TAOUT 


IRTS 


RECIDL 


1 


1 


1 


1 


1 


SR2 


NXTTO 


NXTRO 


TR 


ACKRQ 


RETRY 


TSENT 


STATE 


INRING 


NOTE: ZERO BITS (0) SHOWN ABOVE ARE RESERVED AND SHOULD NOT BE USED. 



NOTES: 

[1] = Set to 1 on power-up or master reset. 

[2] = Non diagnostic mode only (CR17-DIAGC cleared). 

[3] = Any bit set causes host interrupt (INTR goes true) when Master Interrupt Suppress (CR01) is clear. All 
bits are cleared when register is read by the host. 

[4] = Diagnostic State only (CR17-DIAGC set). See diagnostic section for register usage in diagnostic mode. 
CRO — CONTROL REGISTER DEFINITION 



REGISTER 


CR07 


CR06 


CR05 


CR04 


CR03 


CR02 


CR01 


CROO 


CRO 


TXDEN 


TXEN 


RXEN 


ITOKON 


I LOOP 


COPY 


NOINT 


ISOL 



BIT 


NAME 


DESCRIPTION 


CROO 

CR01 

CR02 

CR03 
CR04 


ISOL 

NOINT 

COPY 

I LOOP 
ITOKON 


Isolate. Set true on power up or master reset. Host clears this bit after the host 
memory based WD2840 control block and other WD2840 registers have been set 
up. May be set by the host at any time (will be ignored if WD2840 is in diagnostic 
state). There is some delay for the WD2840 to respond to any state change request. 
A state change to network mode is acknowledged by the state confirmation status 
bit (SR21-STATE) being cleared. Setting ISOL while the WD2840 is in Network State 
will cause a state change to Isolate State, confirmed by an interrupt event (IR00- 
ITM) and the STATE status bit (SR21) being set. This transaction will be delayed 
until the node does not possess the token. Any in-progress frame transmission will 
be completed normally (at the current frame, regardless of queue length), followed 
by a normal token pass sequence. 

Master Interrupt Suppress. When clear, the WD2840 will generate host interrupt 
requests (INTR low) if any bit in the WD2840 interrupt request register (IRO) is set. 
When set, only the interrupt request is suppressed, not the setting of bits in IRO. 
Note that any interrupt request will be dropped by the WD2840 when IRO is read 
since this will clear IRO. 

Enables COPY mode. When set causes all received data frames to be accepted 
and DMA'ed into memory regardless of destination address. (See description in 
Diagnostics Section.) 

Instructs the WD2840 to loop data internally from transmitter to receiver. Used with 
the LOOP diagnostic. Must NOT be set while in network mode (CR00-ISOL clear). 

Enable Token received interrupts. When clear no Token received interrupts are gener- 
ated. When set the WD2840 generates an Itok interrupt when a token is received. 



58 



BIT 


NAME 


DESCRIPTION 


CR05 

CR06 
CR07 


RXEN 

TXEN 
TXDEN 


Receive Data Enable. When clear, the WD2840 still makes normal responses to 
supervisory frames (scan, token pass), but will not DMA any data frames into 
memory and ignores the receiver buffer chain. However any data frame which is 
addressed to this node and for which an ACK is requested, will be NAK'ed with a 
"receiver not enable" Nak code. When RXEN is set, it allows the receiver to DMA 
appropriate data frames into memory. RXEN may be arbitrarily set and reset while 
in Network State but changes will not affect any frames in progress. 

NOTE: Even when RXEN is clear, the WD2840 is "following" the receiver buffer 
chain with an internal register pointing either to the next available buffer (NXTRO 
set) or, if the chain is exhausted, to a link field of zero (NXTRO clear). The con- 
straints on host manipulation of the receiver buffer chain are the same regardless 
of the state of RXEN. See the subsequent section on Receiver Memory Interface 
for more details. 

Master Transmit Enable. When clear no transmissions will occur and the transmit 
buffer chain will be ignored. When set, transmission activity is further dependent 
upon TXDEN (CR07). 

NOTE: Even when TXEN is clear, the WD2840 is "following" the transmitter buffer 
chain with an internal register pointing either to the next frame to transmit (NXTTO 
set) or, if the chain is exhausted, to a link field of zero (NXTTO clear). The con- 
straints on host manipulation of the transmitter buffer chain are the same regard- 
less of the state of TXEN. See the subsequent section on Transmitter Memory 
Interface for more details. 

Data Transmit Enable. Has no meaning unless TXEN is set. When set in con- 
junction with TXEN, normal WD2840 transmission of data and supervisory frames 
will occur. When clear and with TXEN set, only data frame transmission will be 
suppressed. That is, token pass and Ack/Nak supervisory frames will still be 
transmitted when appropriate. 

NOTE: The note above for TXEN applies. 



CR1 — CONTROL REGISTER 1 DEFINITION 



REGISTER 


CR17 


CR16 


CR15 


CR14 


CR13 


CR12 


CR11 


CR10 


CR1 
CR1 


DIAGC 
DIAGC 


PIGT 



INIT 



ADRV 
ADRV 


GIRING 
DMAT 



LOOPT 


TOFF 
RAMT 


NEWNA 
NUDIAG 



BIT 


NAME 


DESCRIPTION (CR17 = 0, Network mode) 


CR10 

CR11 

CR12 
CR13 


NEWNA 

TOFF 
GIRING 


Update NA register. When set causes WD2840 to copy the contents of register 
NAR into register NA. The WD2840 clears this bit after the function is complete. 
This mechanism allows the host to define the WD2840's successor in the logical 
ring. The node's next token pass will be to the new NA node. 

NOTE: The normal token pass recovery applies. If the token pass to the new NA is 
not successful, a normal scan sequence will occur where the WD2840 attempts a 
single token pass to each node address in numerical sequence until a successful 
pass occurs or the node's address itself is reached. 

When set causes WD2840 to ignore timers. (This is NOT intended to be used in an 
operational network, but is provided to support network diagnosis.) CAUTION: This 
control bit disables all automatic network error recovery. 

(Not used, Reserved.) 

Get in logical ring. Instructs the WD2840 to gain entry into the logical ring at the 
next opportunity (i.e. respond to a token pass). The INRING status bit (SR20) is 
confirmation; when INRING is set, it indicates that the WD2840 is participating in a 
logical ring of at least two nodes. If the host clears GIRING while INRING is set, 
the WD2840 will not accept the next token pass to it at which time INRING will be 
cleared as confirmation. 



59 



D 
10 

00 

J* 
o 



BIT 


NAME 


DESCRIPTION (CR1 7 = 0, Network mode) 


CR14 
CR15 

CR16 
CR17 


ADRV 
INIT 

PIGT 
DIAGC 


Address Driver Enable. Enables the sixteen output address (A0-A15). If ADRV = 0, 
the outputs are tri-state and are in Hl-Z, except when DACK goes low. If ADRV = 
1, the outputs are always TTL levels. 

Network Initialization Enable. When clear, the WD2840 will not attempt to 
(reinitialize the network if the net dead timer (TD) expires. When set, TD timer 
expiration causes the WD2840 to enter Scan Mode. In this mode it transmits a 
token pass frame to each node numerically higher in address, one after another, 
until either network activity occurs (another node responds) or until the node's own 
address is reached. When Scan Mode begins, the first node address used is the 
then current NA (Next Address) node address. This value is derived from and is 
affected by the following actions: 

1 . At transition into Network State it defaults to MA + 1 . 

2. It may be set by the host using the NAR register and the NEWNA (CR10) 
control flag. 

3. Upon receipt of a Scan Mode frame, NA is redefined to MA + 1 . 

The successful initialization of the network by Scan Mode causes NA to be defined 
as the first responding node (hence, this node's successor). 

All node address computations are ascending and circular within the valid node 
address range of 1-254. 

NOTE: Since this network initialization activity comes about because of a timer 
expiration, TOFF (CR11) must be clear. 

If set, instructs WD2840 to piggy back token on last data frame transmitted. This 
request is honored if the last frame is determined as a result of limit TXLT or the 
LAST bit set in the TX-FCB, but not if transmission ends due to the reaching of the end 
of the chain. 

Enables diagnostic mode. In network mode this bit must be zero. 



CR1 — CONTROL REGISTER 1 DEFINITIONS 



BIT 


NAME 


DESCRIPTION (CR17 = 1, Diagnostic mode) 


CR10 


NUDIAG 


Perform a new diagnostic. When set causes WD2840 to perform the selected 
diagnostics. The host initializes the appropriate registers for the particular 
diagnostic and by setting this bit can initiate the test. The WD2840 clears this bit 
after completion of the diagnostic. 


CR11 


RAMT 


Selects internal RAM test if in diagnostic mode. 


CR12 


LOOPT 


Selects Loop Test if in diagnostic mode. 


CR13 


DMAT 


Selects DMA Test if in diagnostic mode. 


CR14 


ADRV 


Address Driver Enable. Enables the sixteen output address (A0-A15). If ADRV = 0, 
the outputs are tri-state and are in Hl-Z, except when DACK goes low. If ADRV = 
1 , the outputs are always TTL levels. 


CR15 


— 


(Not used, Reserved.) 


CR16 


— 


(Not used, Reserved.) 


CR17 


DIAGC 


Enables diagnostic mode. Confirmation of diagnostic mode is via status bit STATE 
(SR21). When DIAGC and STATE are both set, diagnostic functions of CR1 apply. 
When DIAGC is cleared, after the selected set of diagnostics in progress com- 
plete, the WD2840 will transition to the Isolate state. This transition will cause an 
interrupt event (ITM). 



fin 



SRO — STATUS REGISTER DEFINITION 



REGISTER 


SR07 


SR06 


SR05 


SR04 


SR03 


SR02 


SR01 


SROO 


SRO 


LASTF 


SENDACK 


L2 





BSZ3 


BSZ2 


BSZ1 


BSZO 



BIT 


NAME 


DESCRIPTION 


SROO 

SR03 

SR04 
SR05 

SR06 
SR07 


BSIZ 

L2 

SENDACK 
LASTF 


BSIZO — BSIZ3 

Buffer size, defines the buffer size in multiples of 64 bytes (the value ranges from to 
15h- Corresponding to a buffer size of 64 to 1024 bytes in 64 byte increments). This 
value is used internally to define buffer boundaries to allow the chip to link buffers. A 
maximum of 16 buffers may be used for a single frame. 
Not used. 

An internal flag set during frame transmission if the length value of the current 
frame is equal to eight. For normal data frame transmission this means the frame 
has no data field and for transparent frame transmission this means the frame is an 
access control frame. (SCAN FRAME) 

An internal flag set during data frame reception to indicate that the incoming frame 
should be acknowledged (send ack/nak frame). This flag is cleared when the 
acknowledgement has been transmitted. 

An internal flag set during data frame transmission to indicate that the current frame 
will be the last to be transmitted with this token. Five situations can cause this to 
occur: 1) ISOL (CR00) becoming set, 2) TXDEN (CR07) becomes clear, 3) current 
frame flagged (via FCB) to be "last frame," 4) the current token frame count reaching 
the TXLT limit, 5) transmitter under-run detection . Note in particular that the last frame 
in the transmit queue will not cause LASTF to set since it's being last is not known until 
frame end. Also if a piggy-back token is permitted (CR16 set) and no acknowledge is 
requested (via FCXB), the token will be piggybacked on the current (last) data frame. 
LASTF is not cleared until the next data frame transmission begins. 



IRO — INTERRUPT REGISTER DEFINITION 



REGISTER 


IR07 


IR06 


IR05 


IR04 


IR03 


IR02 


IR01 


IROO 


IRO 


ITERR 


IROR 


INS 


ITRAN 


IREC 


ITOK 


ITA 


ITD/M 



The setting of any bit in this register by the WD2840 causes an interrupt request (INTR = low) if NOINT (CR01) 
is clear. The reading of this register by the host clears all bits (and any interrupt request). 



BIT 


NAME 


DESCRIPTION (1) 


IROO 

IR01 
IR02 


ITD/M 

ITA 
ITOK 


Network dead or mode change (dual use). When in Network mode, timer TD ex- 
piring (with TOFF clear) causes this bit to be set to indicate no network activity has 
occurred within the timeout period. Also INRING (SR20) is cleared and, if INIT (CR15) 
is set, the WD2840 will enter Scan Mode (see INIT - CR15 for details). Transition from 
Network or Diagnostic State to the Isolate State will be confirmed by this interrupt. The 
choice between the ITD and ITM interpretations is easily made based on the ISOL 
(CROO) bit. 

Date Frame Transmission Unsuccessful. This interrupt indicates that a transmitted 
data frame with an acknowledge request was not successfully acknowledged. 
Either a NAK or no response after two transmissions will cause this. The exact 
cause can be determined by inspecting the appropriate FSB. 

The token has been received. 



61 



o 

J* 

O 



BIT 


NAME 


DESCRIPTION (1) 


IR03 

IR04 

IR05 

IR06 
IR07 


IREC 

ITRAN 

INS 

IROR 
ITERR 


Data Frame Received. This interrupt signifies that a good data frame has been 
properly received and DMA'ed into the buffer chain. Frames that have been 
received can be identified by following the buffer chain noting the WD2840 frame 
status bytes (FSB). A non-zero FSB (host must clear when queuing free buffers) 
indicates a properly received frame. The host may freely remove all received 
frames from the chain up to but NOT necessarily including the last one posted. 
The last one posted may only be removed if the WD2840 NXTRO (SR26) is set. For 
more details see the explanation for NXTRO. 

Indicates that at least one data frame has been transmitted. The number of frames 
transmitted and the status of each (i.e. ACK/NAK, retry count) is determined by 
following the transmit chain and inspecting frame status bytes (FSB). All trans- 
mitted frames up to but NOT including the last posted may be freely removed. The 
last one posted may only be removed if the WD2840 NXTTO (SR27) is set. For more 
details see the explanation for NXTTO. 

New successor. The WD2840 has identified a new successor in the logical ring. 
This happens when the prior successor either failed to respond to a token pass or 
as instigated by a network scan frame. 

Receiver over-run. The WD2840 ran out of buffers or access to the DMA channel 
was delayed by the host so long as to cause loss of received data. 

Transmitter error. Three abnormal frame transmission cases can cause the ITERR 
interrupt. The causes are "transmitter underrun," "premature end of chain," and 
"exceeded 16 buffers." The frame transmission will repeat once per token until the 
host removes the WD2840 from the network, or the cause of the error is fixed. 



(1) = Non diagnostic mode only. See diagnostic section for register usage for diagnostics. 



SR1 — STATUS REGISTER 1 DEFINITION 



REGISTER 


SR17 


SR16 


SR15 


SR14 


SR13 


SR12 


SR11 


SROO 


SR1 


TAOUT 


IRTS 


RECIDL 


1 


1 


1 


1 


1 



BIT 


NAME 


DESCRIPTION 


SR10 

SR14 
SR15 
SR16 

SR17 


RECIDL 
IRTS 

TAOUT 


(Not used, reserved.) 

Receiver Idle. Indicates the WD2840 has received at least 15 contiguous ones. 

Internal Request To Send. Indicates the transmitter is attempting (successful or not) to 
send either data or flags. If the RTS pin is not tied to ground or WIRE-OR'ED with 
another signal, then IRTS = RTS. 

Timer TA expired. 



62 



SR2 — STATUS REGISTER 2 DEFINITION 



REGISTER 


SR27 


SR26 


SR25 


SR24 


SR23 


SR22 


SR21 


SR20 


SR2 


NXTTO 


NXTRO 


TR 


ACKRQ 


RETRY 


TSENT 


STATE 


INRING 



BIT 



NAME 



DESCRIPTION 



SR20 



SR21 



SR22 



SR23 



SR24 



SR25 



SR26 



INRING 



STATE 



TSENT 



RETRY 



ACKRQ 



TR 



NXTRO 



SR27 



NXTTO 



In logical ring. Indicates the node has had the token and has successfully passed it 
at least once (therefore it is included in a logical ring of at least two nodes). See 
GIRING (CR13) for other comments. 

Mode confirmation. Depending on DIAGC (CR17), the WD2840 is either in Isolate or 
Diagnostic state. When ISOL (CROO) is set, STATE set confirms the WD2840 is not 
in Network State. When ISOL is clear, STATE clear confirms Network State. Note 
any state transition into Isolate State causes an interrupt event to occur (ITM). 

An internal flag. TSENT is set when the WD2840 passes the token. It may have 
been either a piggyback or explicit token pass frame. TSENT is cleared when the 
next frame is received. 

An internal flag which is set when either a data frame or a token pass frame must 
be retransmitted. Data frames are only retransmitted if they have an acknowledge 
request and no response at all occurred. Token pass frames (except Scan) are 
retransmitted if no network activity was detected. Both of these situations are 
detected as a result of a TA timeout. 

An internal flag set during data frame transmission if an acknowledgement is 
requested for the specific frame. If this is the case, the WD2840 pauses to await 
the ACK/NAK response frame; if the TA timer expires before the response, a single 
retry will occur (see RETRY-SR23). ACKRQ is not cleared until the beginning of the 
next data frame transmission. 

An internal flag set when the WD2840 receives a token passed to it. It is cleared 
when the token is passed (or if it is ignored for any reason. For example, piggyback 
token on a bad data frame, TXEN clear, or detection of duplicate tokens in the 
logical ring). 

Internal Receive Buffer Pointer State. Because of the linked list approach used in 
the buffer chains, the WD2840 internal register used to follow the list is either 
pointing to the next buffer in the chain or at the address of the next buffer in the 
chain (prior buffer's link field). The WD2840 will always advance along the chain so 
that it has the address of the next buffer to be used. However, when a zero link is 
encountered, the WD2840 retains the link field address expecting eventually that 
the chain will be extended by the host making the link some non-zero value. When 
the WD2840 actually needs the next buffer, it looks again at the contents of the link 
field expecting it to have been changed (chain extended) to the address of an 
available buffer. The NXTRO bit differentiates between these two situations. When 
set it indicates the WD2840 has the address of the next buffer and that all prior 
frames (denoted by posted FSB's) can be removed from the chain for received 
frame processing by the host. When NXTRO is clear it indicates that the WD2840 
has advanced to a zero link (end of chain). 

NOTE: In this situation, the last posted frame CANNOT be removed from the chain 
for processing since it is the link field of his last buffer that must be set in order to 
extend the receiver buffer chain. 

Internal Transmit Buffer Pointer State. The comments for NXTRO (SR26) apply (in an 
analogous manner) to NXTTO since the transmit buffer chain is handled by the 
WD2840 using an identical scheme. When NXTTO is set it indicates that the 
WD2840 has the address of the next frame to transmit in its internal register. 
However when clear, it indicates that the transmit chain internal register points to 
the link field of the last buffer of the last transmitted frame. This link field con- 
tained zero when first read. For the transmit case, this is a normal situation 
corresponding to no data frames to transmit. 

NOTE: As in the receive case, when NXTTO is set, all previously transmitted frames 
(denoted by posted FSB's) can be removed from the chain for reuse. However, 
when NXTTO is clear it indicates that the transmit chain must be extended by the 
host before removing the very last frame that has been transmitted (posted). 



63 



OTHER REGISTER DEFINITIONS 



a 

ho 
00 

o 



NAME 



DESCRIPTION 



CTRO 



NA 



TA 

TD 

CBP(H,L) 

NAR 

AHOLT 

TXLT 
MA 



Running Limit Counter. Used by the WD2840 for Access Hold-Off Limit (AHOLT) checking and 
Transmit Limit (TXLT) checking. When transmitting data frames CTRO is used for TXLT 
counting; otherwise it is used for AHOLT counting. The counter runs from zero to the 8-bit 
limit value. 

Next Address. This register shows the current (instantaneous) successor node in the network 
logical ring. For validity, the WD2840 should be "in the ring" (see GIRING - CR13 and INRING - 
SR20 for more details). The successor node may be changed for a variety of reasons: 

1. Any attempted token pass that fails twice will cause the WD2840 to attempt to locate a 
new successor by sequentially trying token passes to successively higher node ad- 
dresses beginning with NA + 1. 

2. A received Scan frame will cause NA to be set to MA S 1 . If the next token pass fails case 1 
applies. 

3. The host may arbitrarily redefine NA by using the NAR register and the NEWNA (CR10) 
control bit. At a convenient point the WD2840 recognizes NEWNA, copies NAR into NA, 
then clears NEWNA as confirmation. If the next token pass fails case 1 applies. 

Acknowledgement Timer. Value of maximum allowed time between frame transmission and 
ACK/NAK (if requested), or between token sent and network activity. The delay is in in- 
crements of 64 times the period of the clock CLK. Thus, if CLK = 2 MHz, then TA may be set 
in increments of 32 microseconds (range of 32 /^s to 8.2 ms). 

Network Dead Timer. Value of maximum time interval between received valid frames on the 
network. 32X range of TA. 

Control Block Pointer. A sixteen bit pointer to the WD2840 control block in the user's memory. 
Must not be modified while the WD2840 is in network mode. 

Next Address, Request. Used in conjunction with the NEWNA (CR10) control bit to cause the 
WD2840 to update the NA register. This redefines the node's successor in the network logical 
ring. It MUST be an address in the range 1-254. The acceptance of this update is confirmed 
when the NEWNA control bit is cleared. On the next token pass, if the redefined successor 
fails to accept the token, this WD2840 enters Scan mode where it sequentially attempts a 
token pass to successively higher nodes. 

Access Hold-off Limit. This register is set at a value indicating the number of access cycles 
(tokens received) that must be skipped before the data frame may be transmitted. (A token pass 
frame will be sent even if a data frame may not be sent at a given access cycle.) Initialized to zero 
at power up. 

Transmit Limit. This register is set at the maximum number of consecutive data frames the 
WD2840 may transmit during one access cycle. A value of zero allows the WD2840 to transmit all 
frames queued up to 256. Initialized to zero at power up. 

My Address. The WD2840 receives only frames with this destination address (along with the 
broadcast address) and inserts this address into the SA field of any transmitted frame. Must 
be set by the host (range is 1 to 254). 



64 



1.4 DIAGNOSTIC AIDS 

There are three levels of diagnostics supported by 
the WD2840; those that are associated with the 
network as a whole, those associated with the in- 



DIAGNOSTIC 
MODE CONTROL 


DEFINITION 


CROO 
ISOL 


CR17 
DIAGC 


SR21 
STATE 


1 








WD2840 "Isolated." Power- 
up condition or isolate 
request. 











WD2840 active. 


1 





1 


Isolate request function 
confirmed. 


1 


1 





Host request to enter 
diagnostic mode. 


1 


1 


1 


Diagnostic mode con- 
firmed. Diagnostic func- 
tions of CR1 apply. 








1 


Illegal. 





1 





Illegal. 





1 


1 


Illegal. 



dividual node, and those that are limited to the 
WD2840 as a device. These tests are Network 
Diagnostics, System Diagnostics and Self Diagnos- 
tics respectively. The Network Diagnostics can be 
performed while the WD2840 is in the logical ring, but 
the System Diagnostics and the Self Diagnostics 
may be used only while the WD2840 is in the 
diagnostic mode. 

Diagnostic mode may be entered after power-up or 
from the network mode by manipulation of the mode 
control bits. The mode transition is confirmed by the 
WD2840 via the STATE status bit. 

Once in diagnostic mode, the desired test is selected 
via CR1. Because most of registers 8 through F are 
interpreted differently for each test, only one of the 
diagnostic test bits should be set at a time. In 
conjunction with setting the diagnostic bits, the 
NUDIAG (CR10) bit must be set to perform the 
diagnostic test requested. 

At the completion of the selected test NUDIAG is 
cleared by the WD2840. Therefore the host can initi- 
ate a diagnostic by entering the diagnostic mode, ini- 
tializing the proper registers, setting the desired 
diagnostic bit, and setting NUDIAG. The host then 
moniters CR1 for NUDIAG going to zero, indicating 
the completion of the requested diagnostic. 



O 
to 
oo 

o 



DIAGNOSTIC STATE FLOW CHART 



( power-up) 




TO NETWORK STATE 



INTRPIN43 
GOES LOW 




LOOP 
TEST 



NUDIAG -0 
(CR10) 



Poll CR1 forO in 
NUDIAG for test 
complete, process 
results, then clear 
DIAGC in CR1 to exit or 
set NUDIAG and NEXT 
TEST to continue 
diagnostics. 



65 



D 

00 
£* 
O 



ITM INTERRUPT 




Figure 1.3 FUNCTIONAL STATES 



1.4.1 SELF DIAGNOSTICS 

Internal Ram and Interrupt Test 

There are nine eight bit registers in the WD2840 
which are not directly accessable by the users CPU. 
This test provides a means to check those registers 
and the interrupt register. The contents of register A 
are placed into the interrupt register and five even 
internal registers, and the contents of register B in 
four odd internal registers. The nine registers are 
then added together without carry and the result is 
placed in registers 2, 5, 6, 7. 

Use the following procedure to initiate the RAM test: 

1. Enter diagnostic mode. 

2. Set up registers A and B 

3. Set RAMT. 

4. Set NUDIAG (can be set with RAMT bit together). 

5. Wait for NUDIAG to be cleared. 

6. Read registers 2, 5, 6, 7. Clear RAMT. 

Note that the setting of any bit in the interrupt 
register while NOIN T is clear will generate a hard- 
ware interrupt (INTR , pin 43 goes true). 

1.4.2 SYSTEM DIAGNOSTICS 

DMA Test 

This test verifies proper operation of the DMA sub- 
system by reading the value from a register and 
writing it into the user memory. The test continues by 
reading the value from the same location in memory 
and writing it into another register. 

The value is read from register C. Using the transmit- 
ter DMA sub-system, it is written into memory loca- 
tion addressed by register A and B (location N; 
register A is the MSB). The receiver DMA sub-system 
is used and contents of the same address is read and 
it is stored into the register 7. Next the receiver dma 
is used and the contents from register D is written 
into location N + 1. The transmitter dma reads the 
value from location N + 1 and stores it into register6. 

It is the host's responsibility to check if the contents 
of registers C and register 7 and memory location N 



match. The same is true for registers D and 6 and 
memory location N + 1. 
Loop-Back Test 

The host can test the WD2840 transmitter and receiver 
logic by using the Loop Test. 

There are two Loop Tests available for diagnostic pur- 
poses — internal and external. 



(CR12) 
LOOPT 


(CR03) 
1LOOP 


DEFINITION 





1 
1 



1 


1 


Not in Loop Test 

Do not use in network mode 

External loop 

Internal loop 



When using the external loop the interface or modem 
must have the necessary logic to tie TD to RD and TC 
toRC. 

Use the following procedure to run the loop test. 

1 . Set up a 256 byte transmit buffer with the data pat- 
tern to be transmitted. 

2. Initialize a 256 byte receive buffer with all "00s" or 
"FFs." 

3. Load register A (MSB) and B (LSB) with the address 
of the transmit buffer. 

4. Load register C (MSB) and D (LSB) with the address 
of the receive buffer. 

5. Load register for Internal or External Loop. 

6. Load register 1 for diagnostic & loop. (85h) 

7. Refer to Diagnostic State Flow Chart. 

NOTE: 

If this test frame is allowed onto the network, trans- 
mission collisions may occur. Further, the first three 
bytes of the transmit buffers will be interpreted as 
TC, DA and SA, respectively, by the other stations. 
Therefore in case this test is initiated while this node 
is in the logical ring, care should be taken for 
choosing these three values for external loop-back 
test. 

For p roper operation of the internal loop-back test the 
CTS and SQ pins of the W D2840 should be either tied 
to ground or tied to RTS pin of the WD2840. 



66 



1.4.3 NETWORK DIAGNOSTICS 

Duplicate Station Detection 

Duplicate stations (more than one station with the 
same address) can result from the faulty program- 
ming of internal register MA (due to wrong address 
switch settings on the user's device, for example). 
This is expected to occur often enough to warrant the 
addition of a detection algorithm in the users 
WD2840 initialization procedure. 

After initialization, the user should place the WD2840 
in the network mode with TXEN off and ITOKON on. 
This will cause the WD2840 to generate an ITOK inter- 
rupt each time a token is passed to its address (MA). 
The host must provide the timeout algorithm which 
should be greater than the maximum time for the 
network to pass the token around the ring twice. Check- 
ing twice eliminates the possibility that the Network is 
in the scan mode and sending tokens to non-existing 
stations. 

It is useful to note that this constraint requiring each 
node which is participating in the network logical 
ring to have a unique address does not extend to 
nodes which are "listening" but not "in the ring." It 
might be useful to a network designer to have groups 
of receive only nodes which have the same node 
address but do not participate in the network token 
passing (see GIRING - CR13). Data frames transmit- 
ted to such clusters must not request acknowl- 
edgement since all nodes in the cluster would 
simultaneously respond. 



Copy Mode 

The COPY Mode is selected by setting the COPY 
control bit (CR02). Normally the WD2840 receives 
(DMAs into the receive buffer chain) data frames only 
if they contain the general broadcast destination 
address or if they are specifically addressed to the 
WD2840. This occurs when the frame's destination 
address (DA) matches the WTJ2840 my address (MA, 
set by the host). 

However, when COPY mode is selected data frames 
which are specifically addressed to other nodes will 
be treated as broadcast frames by this node. The 
COPY mode allows a specific node to "eavesdrop" on 
data frame traffic on the network. 



Nak Response 

The WD2840 sends negative acknowledgements 
(NAK's) on response to received frames under 



several circumstances. The NAK prevents the 
transmitting node from wasting bandwidth retrying 
indiscriminately, and further, lends visibility to in- 
dividual network node problems. The NAK includes a 
reason code which is available to the transmitter's 
software (via the TFSB). 

Each data frame to be transmitted can be specifically 
marked (via the FCB) by the host to require an 
ACK/NAK response from the receiving WD2840. In 
the absence of errors, an acknowledge (ACK) frame 
will be returned to the transmitter as confirmation. 
However, several circumstances cause a Negative 
Acknowledge (NAK) to be returned: 

1 . Insufficient buffer space 

2. Receiver not enabled (RXEN - CR05 cleared) 

3. Receiver overrun 

4. Frame exceeded 16 buffers in length 

This information is placed in the transmitted 
frames's FSB. See section 2.1.2 for more details on 
the Transmit Frame Status Byte (TFSB). 

2.0 INTERFACES 

There are two interfaces to the WD2840: the host 
computer side, and the network side. The network 
side is conventional from an electrical point of view, 
the WD2840 performs all logical functions required to 
ensure communications capability on broadcast 
media (such as coax or RF). 

The host interface involves two separate functional 
interfaces: the status/control registers described in 
section one, and a DMA interface that is described in 
the following subsection. 

2.1 HOST 

The WD2840 uses a complex memory buffer architec- 
ture allowing it to respond in real time to its network 
obligations (e.g., to meet network data rate and pro- 
cessing delay requirements). These memory struc- 
tures are managed cooperatively by the host and the 
WD2840. 

Memory management functions requiring real time 
response (e.g., traversing chains) are completely 
handled by the WD2840. Other important, but not 
time critical operations are the responsibility of the 
host software (such as removing used buffers from 
the transmit chain). 

All memory references by the WD2840 are pointed to 
by memory locations (and internal registers) initially 
defined and set up by the host software. Initial values 
and memory based registers are grouped together 
and called the WD2840 Control Block. 



O 
oo 

O 



67 



The location of this control block is written into the 

< registers CBPH and CBPL anytime the WD2840 is in 

q Isolate State. This control block has the following 

,IO structure: 
00 



CBP^ +0 


NXTR(H) 


Receive Buffer Chain 
(MSByte) 


+ 1 


NXTR (L) 


Receive Buffer Chain 
(LSByte) 


+ 2 


NXTT (H) 


Transmit Buffer Chain 
(MSByte) 


+ 3 


NXTT (L) 


Transmit Buffer Chain 
(LSByte) 


+ 4 


BSIZE 


Buffer Size / 16 (0-F = 64- 
1024 bytes) 


+ 5 


EVTO 




+ 6 


EVT1 


Eleven separate Event 
Counters, see section 
2.1.1 for details 


+ F 


EVT10 





As the WD2840 transitions to Network State, it reads 
and uses the first five bytes of the control block. The 
remaining eleven bytes of event counters are ac- 
cessed by the WD2840 only when each specific event 
condition occurs. 

Either the Receive (NXTR) or Transmit (NXTT) chain 
entries in the control block may initially be zero; in 
such a case the WD2840 expects the chain to be 
extended by the host's changing the zero link field in 
the control block. Thereafter any such zero link would 
be in a buffer. 

The WD2840 uses constant size buffers; their length 
is set by the value in location BSIZE. The buffer size 
is indicated by a 4-bit count in the least significant 4 
bits of the BSIZE byte in the WD2840 control block. 
The buffer sizes available are multiples of 64; 
(BSIZE +1)64 is the buffer size used by theWD2840. 
Thus a BSIZE range of 0-15 corresponds to actual 
buffer sizes of 64 through 1024 bytes. This buffer 
length is inclusive of control bytes and buffer link 
pointers. 

The WD2840 includes a chained-block feature which 
allows the user more efficient use of memory, par- 
ticularly in situations where the maximum packet 
size is much larger than the average packet size. One 
or up to 16 buffers may make up a frame but a buffer 
may not contain more than one frame. 

Byte counters are associated with each frame (at the 
memory interface, not actually transmitted within the 
frame) so that frames on the network need not be 
integer multiples of buffers. The byte counters include 
all buffer management overhead. Therefore, a frame 
consisting of 100 transmitted data bytes, occupying two 
64-byte buffers, would have a byte count of 110 (six 
bytes per frame + 2 bytes per buffer). 

Since the WD2840 receive and transmit buffer chains 
are linked lists (see section 2.1.2 and 2.1.3) and are 
"followed" by the WD2840 but managed by the host; 



it is expected that the host will maintain both a FIRST 
and a LAST address for each chain. On transition into 
Network State, the chain origin information in the 
WD2840 control block is the same as FIRST. In fact, 
since the WD2840 does not change these control 
block entries, they can be maintained directly as 
FIRST by the host. An explicit LAST could be placed 
in an extended control block section. 

The WD2840 "follows" the linked buffer chains by 
maintaining a NEXT address internally for each 
chain. This NEXT address can be in one of two 
states: 1) it can be the address of the next buffer in 
the chain, or 2) at the chain end (zero link), it can be 
the address of the buffer containing the zero link. The 
WD2840 uses a status bit for each chain, NXTR0 
(receive) and NXTT0 (transmit), to differentiate the 
two states. When set they indicate the WD2840 chain 
NEXT address is in state 1 above; when clear they 
indicate state 2 above. This is an important distinc- 
tion since it indicates whether the last buffer posted 
in a chain can be removed by the host (because the 
WD2840 has advanced to the buffer beyond) or must 
be left until the chain can be extended so the 
WD2840 can advance. 

The host software monitors the progress of the NEXT 
pointer, and updates FIRST and LAST as it adds (and 
removes) buffers to (from) the chains as required. The 
WD2840 provides Interrupt Events (see IR0) and 
NXTR0, NXTT0 status bits to indicate when it ad- 
vances along the two chains and exactly what state 
its NEXT address registers are in. The operation of 
these chains will be explained by example in later 
sections. 

"Deadly Embrace" Prevention 

A "Deadly Embrace" can occur when two processors 
reach a state where each is waiting for the other. In 
this case, the two processors are the user's CPU and 
the micro-controller inside the WD2840. Therefore, to 
prevent the "deadly embrace," the following rule is 
obeyed by the WD2840 and should also be obeyed by 
the user's CPU. This rule applies to the WD2840 
memory registers and to the I/O registers. The Event 
Counters are an exception to this rule. 

Rule: 

If a bit is set by the CPU, it will not be set by the 

WD2840, and vice versa. If a bit is cleared by the 

WD2840, it will not be cleared by the CPU, and vice 

versa. 

As an example, the NEWNA (CR10) control bit is only 
set by the host and is only cleared by the WD2840. 

Dual DMA 

The WD2840 may, for efficiency, interleave frame data 
fetch/store operations with fetches and stores of 
pointers and flags in memory. In all cases, operation 
sequencing is such as to prevent deadlocks and 
ambiguities between the WD2840 and software. 



68 



2.1.1 EVENT COUNTERS 

Several non-fatal logical events are tabulated by the 
WD2840 and made visible to the host via memory 
based event counters (see WD2840 control block 
organization for specific locations). The WD2840 will 



increment each counter at the occurance of the 
specified event. Note that the WD2840 will not in- 
crement past 255. The host has the responsibility of 
initializing each counter. 



O 
ro 
oo 

o 



COUNTER 



DESCRIPTION 



EVTO 
EVT1 

EVT2 

EVT3 
EVT4 

EVT5 

EVT6 



EVT7 



EVT8 



EVT9 
EVT10 



"Set scan mode" frame received from the network. The NA register was redefined to 
MA + 1 at the time. 

Transmission error first attempt, second try successful. Can only occur for frames 
requiring an acknowledgement. It indicates no response was received for the first 
transmission; however, the second transmission was either ACK'ed or NAK'ed. 

Transmission error. Attempt aborted due to either transmitter underrun or frame 
length exceeding 16 buffers. 

Timer TD (network dead) expired. 

Access Control Frame Reception Error. A one or two byte supervisory frame 
(ACK/NAK, Token Pass, Scan Mode) has been received in error. This may be due to an 
FCS error, frame abort, or carrier loss detection. 

Data Frame Reception Error. An incoming data frame was incorrectly received due to 
an FCS error, frame abort, carrier loss detection, or receiving a data frame when ex- 
pecting an ACK/NAK frame. 

NAK sent. Can occur for any of the following reasons: 

1. Insufficient buffers in chain 

2. Receiver not enabled (RXEN clear) 

3. Receiver overrun 

4. Frame length exceeded 16 buffers 

Invalid frame received. Caused by the detection of certain abnormal network con- 
ditions such as receiving an ACK/NAK frame when not expecting one, receiving a 
Scan mode frame when expecting an ACK/NAK frame, or receiving an invalid 
supervisory frame. 

Duplicate token detected. This counter will be incremented when the WD2840 
determines that more than one token exists in the logical ring. This happens if a 
token pass is received when the WD2840 already has the token, or a data frame is 
received when the WD2840 is waiting for an acknowledgement frame. 

Not used. 

Duplicate node address. This counter will be incremented when a data frame being 
DMA'd into memory has a source address (SA) equal to the WD2840 node address 
(MA). This counter when used with COPY mode (CR02) is one way for detecting other 
nodes with the same node number (MA). 



2.1.2 TRANSMIT MEMORY INTERFACE 

When the token is received, data transmission is 
enabled (TXEN - CR06 and TXDEN - CR07 both set), 
and if the access hold-off counter has reached its 
limit, the WD2840 will determine whether any data 
frames are pending in the transmit chain. If so, it will 
transmit the first data frame in the chain. Otherwise 
the token will be passed. A given data frame will be 
the last frame transmitted for this token if any of 
several conditions occur: 

1. ISOL (CROO) is set indicating the host has 
requested a transition to Isolate State. 

2. TXDEN (CR07) is clear indicating the host has 
changed data frame transmission rights. 

3. The frame FSB indicates this frame should be the 
last transmitted for this token. 



4. The running frame counter has reached its limit 
(TXLT). 

5. No further frames are pending in the transmit 
chain. 

If any of the first four reasons above are true a token 
pass will occur. If the last frame does not require an 
acknowledgement, the WD2840 will piggyback the 
token pass if that is permitted (CR16). If the token 
cannot be piggybacked or if the last frame trans- 
mitted is the last frame pending (condition #5 above), 
an explicit token pass will occur. A piggyback token 
will not occur for the last pending frame because, for 
the general multiple buffer case, it is not known to be 
the last pending frame until after the transmission is 
complete. 



69 



5> 
O 
10 

00 

J* 

O 



TheWD2840 will read and evaluate the address of the 
next frame at two specific points in time: 

1. At the end of the prior frame, even if the prior 
frame is the last to be transmitted for this token. 

2. When the token is received and data frame 
transmission is permitted. 

If a non-zero frame address is found at time 1 above, 
it is kept and used without being re-read at time 2 
above. However, if no pending frame is found at time 
1, this is noted with the NXTTO flag clear and the 
chain re-inspected on each occurrence of time 2 
above. 

As frame transmission commences, the WD2840 
reads the address of the next buffer, the frame 
control byte, (FCB) and the frame length. It then 
starts reading bytes from the buffer and sending 
them until the frame length count or the end of the 
buffer is reached. The new buffer is read and data 
transmitted as before. (See Figure 2.1) 

The frame length provided in the LENGTH field must 
be the sum of the overhead bytes and number of data 
bytes (see Fig. 2.1). 

Simplified formula for LENGTH: 

LENGTH = # of data bytes + 2 link bytes per buffer 
+ 6 overhead constants per frame. 

Example #1 

LENGTH = 8 (0010h in LENGTH field) 

implies one buffer is used for this frame (64 bytes) 
two link + six overhead, no data. 

Example #2 

LENGTH = # of data bytes + 2 link bytes per buffer 
+ 6 overhead constants per frame. 

Programmed buffer size = 64 bytes per buffer. Two 
buffers are used in this frame for a total of four link 
bytes (2 per buffer), six overhead, and 57 data bytes. 

The General Formula for LENGTH 

WHERE 

Nq = # of data bytes (max 4095) 

6 = Overhead Constant per frame (FSB, FCB, 
LENGTH (H), LENGTH (L), DA, SA) 

B« = B SIZE in bytes (64, 128, etc.) a constant 
preprogrammed into the WD2840 on 64 
byte boundaries to a max of 1024 bytes. 

GIVEN Nq 

L = Nq + 8 + 2*TRUNC 
GIVEN L 

#B's = 1 + TRUNC 



Examples: Find L given Nq 
N D 



Np + 5 
BK-2 



L - 1 



BK 
ND = L - 6 - 2(#B's) 

NOTE: 

The expression for Np fails for values of L = B« + 1 . 
This is okay since the 2840 doesn't generate such 
values. 








8 






1 


9 


1 bufr 




56 


64 




B|< = 64 


57 


67 


2 bufrs 




118 


128 






119 


131 


3 bufrs 




120 


128 


1 bufr 


Bk = 128 


121 


131 


2 bufrs 




246 


256 






247 


259 


3 bufrs 


Find#B's, 


Nq given L 








L 


#B's 
1 


No 




8 







9 


1 


1 


Bk = 64 


64 


1 


56 




67 


2 


57 




128 


2 


118 




131 


3 


119 




L 


#B's 

1 


No 




128 


120 




131 


2 


121 


Bk = 128 


256 


2 


246 




258* 


3 


246 




259 


3 


247 



*NOTE: 

Case corresponds to buffer end and frame end on 
same byte . . . extra buffer consumed. 

When the frame length is finally reached, the 
WD2840 pauses if an acknowledgement has been 
requested. The frame status byte (FSB) is updated 
when the frame is completed; its posting indicates 
frame completion and gives information about the 
success or failure of the frame transmission. At 
frame completion, the WD2840 attempts to advance 
along the transmission chain to identify the next 
frame regardless of whether it will be transmitted 
with this token or later. 

The host may add frames to the end of the transmit 
chain at any time by changing the zero link in the last 
buffer. Also buffers of all posted frames up to but 
NOT including the last buffer of the most recently 
posted, may be arbitrarily removed from the chain. 
The last posted frame (more specifically, the last 
buffer of the last frame) may only be removed and 
reused if NXTTO is set. This indicates that the 
WD2840 has advanced its NEXT address to the next 
frame but that its transmission has not been com- 
pleted (in fact, perhaps not even started). 

NOTE: 

The WD2840 checks only the most significant byte of 

the link field for zero link detection. This has the 

following implications: 

1. When writing into a zero link field, the host must 

write the LSB of the new link field first, followed by 

the corresponding MSB. 



70 



2. All buffers must have a starting address greater 
than or equal to Hex '0100'. 

TRANSMIT FRAME STATUS BYTE (WRITTEN BY WD2840) 



BIT# 


7 


6 


5 


A 


3 


2 1 


Name 


DONE 


WIRING 


X 


X 


SELF 


VAL2 VAL1 VALO 



BIT 


NAME 


DESCRIPTION 


7 
6 

5-4 
3 

2-0 


DONE 
WIRING 

SELF 
VAL 


Set to guarantee a non-zero value for the posted FSB. 

Value of the corresponding bit in received ACK frame. 

Reserved. 

When set, indicates the ACK/NAK code appears in the value field (bit 2-0) of this 
FSB is assigned by the WD2840 transmitter routine. When clear, indicates value 
resulted from ACK/NAK code from receiving station. 

An encoded field whose interpretation depends upon the SELF flag (bit 3) in this 
FSB. 

a. SELF clear 

— No receive error ( = ACK when DONE is set). 

1 — Insufficent buffers for frame. 

1 — Receiver not enabled at frame start. 

1 1 — Receiver over-run. 

1 — Frame exceeded 16 receive buffers. 

b. SELF set 

— No transmit error. 

1 — Transmission failed after retry. 

10 — Transmission under-run. 

1 1 — Premature end of chain. 

10 — Transmission frame exceeded 16 buffers. 



Transmit Frame Status and Control Bytes 

Each frame has two bytes reserved, one for host 
control information needed by the WD2840, the other 
for status information posted by the WD2840 at frame 
transmission completion. The frame control byte 
(FCB) is only read by the WD2840, never changed; the 
frame status byte (FSB), is written (posted) by the 
WD2840 with no regard for its prior contents. On 
completion, the FSB value will always be non-zero; it 



is important that the host zero the FSB byte in order 
to be able to recognize a posted frame. 

NOTE: 

Specifically note in Figure 2.1 that the first buffer of 
each frame has a different structure than any over- 
flow buffers for that frame. In particular, each frame 
has only one set of FSB, FCB, and LENGTH fields 
regardless of the number of buffers required by the 
frame. 



TRANSMIT FRAME CONTROL BYTE (WRITTEN BY HOST) 








BIT# 


7 


6 


5 


4 


3 


2 


1 





Name 


WACK 


FCBLF 


TRANSP 


X 


X 


X 


X 


X 



BIT 


NAME 


DESCRIPTION 


7 

6 
5 

4-0 


WACK 

FCBLF 
TRANSP 


Wait for Acknowledgement. Instructs the WD2840 to wait for an ACK/NAK 
response from the receiver for this particular frame only. The token control (TC) 
byte in the frame is automatically set to cause the destination node to respond. 
This bit must NOT be set if the frame uses the broadcast destination address. 
Inadvertently doing so will cause the frame to be posted "Transmission failed, due 
to max retries." 

Last Frame. This bit will cause the WD2840 to pass the token either piggybacked 
with this frame (if possible) or explicitly after the frame transmission completes. 

Transparent Frame. This bit will cause the WD2840 to interpret the buffer contents 
to be the exact sequence of bytes to be transmitted. The normal token control (TC) 
byte and source address (SA) byte generation is suppressed. Note that for a non- 
transparent data frame the TC byte must NOT appear in the buffer. 

Reserved. 



o 
to 

00 

o 



71 



o 
ro 

00 

o 



















END 

OF 

CHAIN 




NXTT(H) 
NXTT(L) 




INTERNAL REGISTERS 












LINK(H) 




LINK(H) 
LINK(L) 




LINK(H) 
LINK(L) 





XX 


LINK(L) 






FSB 
FCB 




FSB 
FCB 




LENGTH (H) 
LENGTH (L) 


LENGTH (H) 
LENGTH (L) 


DA 


DA 


SA 


SA 


D 
A 

T 
A 


D 
A 

T 
A 




TRANSMITTE 
ANDR 


ED BUFFERS, 
E-QUEUEDBY 


TO BE REFILLED TO BE TRANSMITTED 
THE HOST 

Figure 2.1 TRANSMIT BUFFER CHAIN 


) 



2.1.3 Receive Memory Interface 

After the third byte of an incoming data frame is 
detected, the WD2840 will begin to place frame data 
into memory if several conditions are satisfied: 

1. Receiver Enabled (RXEN-CR05 set). 

2. There is an available buffer in the receive buffer 
chain. 

3. The frame is addressed to this node specifically, 
it is a broadcast frame, or COPY mode has been 
selected by the host. 

As the frame continues, it may completely fill its 
buffer. If this happens the WD2840 reads and in- 
spects the link field of the current buffer. If this link is 
zero, an error occurs and the receive chain is reset to 
reuse from the first buffer used by the dropped frame. 
However, if another buffer is available, the incoming 
frame is continued beginning in the third byte of that 
buffer. This continues until one of several things 
happen: 

1. Receiver overrun. The WD2840 has a four byte 
FIFO to buffer incoming frame data; however, if 
the host DMA responds too slowly a receiver 
overrun will occur. If this happens an event 
counter is incremented, the frame is dropped, 
and the receiver buffer chain is reset to reuse 
buffers of the dropped frame. 



2. Current buffer capacity exhausted. If 16 buffers 
have been used for the current frame, an event 
occurs with the frame being dropped and the 
chain reset. Otherwise the WD2840 attempts to 
advance to the next buffer in the receiver buffer 
chain. The frame data will be continued in this 
subsequent buffer. If the end of the receiver 
buffer chain is reached an event counter is 
incremented, the frame is dropped, and the 
chain reset. 

3. Frame ends. If the FCS is not correct an event 
counter is incremented, the frame is dropped, 
and the chain is reset. If correct however, the 
frame length is placed in the LENGTH field and 
the Frame Status Byte (FSB) is posted "done, no 
error." 

If the frame is addressed to this node and indicates 
an acknowledgement is required (TC = 255), whether 
or not an error occurs, the WD2840 responds with an 
ACK/NAK supervisory frame indicating either 
success or failure. In case of receiver over-run, bad 
FCS, and SA= MA acknowledgement request will be 
ignored. (See section 1 .4.3 for details) 

It is the host's responsibility to ensure that buffers 
are available, initialized (FSB zero'ed), and attached 
to the end of the receive buffer chain. 



72 



RECEIVE FRAME STATUS BYTE (WRITTEN BY WD2840) 



BIT# 


7 


6 


5 


4 


3 


2 


1 





Name 


DONE 


X 


X 


X 


X 


X 


X 


X 



BIT 


NAME 


DESCRIPTION 


7 
6-0 


DONE 


Set to indicate the frame reception is complete. 
Reserved. 



o 

IO 
00 

o 



RECEIVE FRAME CONTROL BYTE (WRITTEN BY HOST) 



BIT# 


7 


6 


5 


4 


3 


2 


1 





Name 


X 


X 


X 


X 


X 


X 


X 


X 



BIT 


NAME 


DESCRIPTION 


7-0 


— 


Reserved. 



2.2 MODEM INTERFACE 

The modem interface is the conventional half duplex 
NRZ type with separate data and clock (Figure Z3J. 
When the WD2840 de sires to transmit, it asserts RTS 
and awaits CTS. RTS is generally used to enable the 
modem transmitter. After a system depen dent 
preamble is generated, the modem asserts CTS 
which allows the WD2840 to begin the actual trans- 
mission of the frame. (Note: CTS may be asserted 
permanently if the transmission system does not 
need to generate a preamble). 



The SQ input is used on receive to indicate a valid 
carrier. If this term is negated anytime during a 
receive message, the WD2840 will presume the 
message is in error and treat it as an abort. This 
signal is used to augment message integrity beyond 
that of the CRC by allowing a modem to detect and 
report low level faults (such as out-of-frequency 
carrier or missing clock). 




INTERNAL REGISTERS 



LINK(H) 
LINK(L) 




LINK(H) 
LINK(L) 




FSB 

FC B 




LENGTH(H) 
LENGTH(L) 


DA 


S A 


D 
A 
T 
A 



LINK(H) 
LINK(L) 










XX 







END 

OF 

CHAIN 



FILLED BUFFERS, TO BE EVALUATED BY THE HOST AVAILABLE FOR WD2840 USE 

Figure 2.2 RECEIVE BUFFER CHAIN 



73 



o 
10 

00 

x* 

o 



DATA/ 

CLOCK 

ENCODER 



L> 



TRANSMISSION 

— is — 



CTS 



OPTIONAL 

PREAMBLE 

DELAY 



{> 



DATA/ 

CLOCK 

ENCODER 



SQ 



TRANSMIT | RECEIVE 



Figure 2.3 CONCEPTUAL MODEM 



3.0 NETWORK PROTOCOL 

To enable operation on a broadcast medium without 
the need for a central controller performing device 
polling, the VVD2840 implements a media access 
protocol. The particular access protocol designed 
into the WD2840 prevents self-induced transmission 
collisions and ensures a fair and guaranteed 
distribution of transmission time among attached 
controllers. (See Appendix A for Protocol flowcharts.) 

This design-out of collisions allows the WD2840 a 
greatly expanded selection of transmission media, 
since no physical characteristics of a particular 
medium are relied upon for proper network operation. 
Another benefit of this lack of collisions is the 
visibility of network faults. If a collision is detected, it 
is treated consistently in a error recovery mode by 
the WD2840 and is also unambiguously visible to 
service personnel as a fault. 

Secondly, the WD2840 can ensure that a transmitted 
message was correctly received and buffered by 
requiring acknowledgement of its receipt. This is 
sometimes called "acknowledging datagrams" 
where the sender awaits a predefined period after a 
frame is sent for a reply from its destination. With 
this method, no sequence counters nor multi-frame 
retransmission buffering is required. The scheme is 
efficient since local network applications such as the 
WD2840 address do not encounter extremely long 
transmission delays (such as satellite links) as in 
conventional data networks (such as X.25). 



Both functions are parameterized, allowing tuning 
and optimization by the user to his unique ap- 
plication. These parameters may be adjusted in real 
time by the user's software, allowing a dynamic 
network, responsive to constantly changing 
requirements. 

The two functions, access control and data transmis- 
sion, function simultaneously though independently. 
Thus they are described separately as subprotocols 
for clarity. 

3.1 Data Transmission 

The data transmission cycle is entered after the 
token has been received and data transmission rights 
validated (see section 3.2 "access method"). The 
WD2840 determines if there is a frame to be sent and, 
if not, simply sends the token to the next station. 

If something is queued for transmit, the WD2840 
DMA's it from memory and sends it. After the 
complete frame has been sent, the WACK (Wait for 
ACK) bit is tested in the TFSB (Transmit Frame Status 
Byte). If set, the WD2840 waits for, and expects, an 
acknowledgement from the frames recipient. A timer 
(TA) is started. In the normal case, the ACK is 
received before TA expires which causes the WD2840 
to send the next frame queued, repeating this 
procedure. Thus, the WD2840 sends multiple frames 
to various destinations until the transmit queue is 
emptied or a programmed limit (register TXLT) is 
exceeded. 



74 

























MA = 4 






MA = 11 






MA = 27 






NA = 11 






NA = 19 


1 




NA = ** 




♦ 






















MEDIUM 
















O C "I 


















Y 




MA = Node ("My") Address 





















MA = 54 
NA = 4 


"* 


MA = 19 
NA = 54 




NA = Next (Successor) Address 
** = does not apply 




Figure 3.1 


TOKEN PASSING ON A LOGICAL RING 





o 

00 

o 



In the event TA expires, the frame is re-transmitted 
once. (Note: it is the responsibility of higher level 
protocol operating in the host to protect against the 
possibility of duplicate frame reception.) If TA expires 
again, usually indicating the destination node is off- 
line, the FSB is updated to reflect the unsuccessful 
transmission, interrupt bit ITA is set, and the frame is 
skipped. 

A frame is also skipped and tagged if the destination 
station sends a NAK, indicating it cannot presently 
process the frame. 

TRANSMISSION OF ABORT 

An ABORT is transmitted by the WD2840 to term- 
inate a frame in such a manner that the receiving 
station will ignore the frame. An ABORT is sent when 
there is a Transmitter Under-Run. The abort sequence 
is a zero, followed by seven ones, after which RTS is 
set false. 

3.2 ACCESS METHOD 

The WD2840 network access method is based on the 
use of tokens, the specific granting of transmission 
rights passed from station to station. At any given 
time, exactly one station has the right to transmit 
(this right is called the token) and is obligated to pass 
it on when finished with it. 

This can be clarified by referring to Figure 3.1. We 
assume in this figure that the network has already 
been initialized (meaning that the linkages in the 
access ring have already been established) and the 



token is held at this instant by station 4 (the station 
whose MA register = 4). 

When station 4 is ready to pass his access right on, 
he sends a message to the station number called out 
in his internal register NA, in this case 11. The 
message, and thus the token, are received by station 
11 who can now transmit its message(s). When 
station 11 is ready to pass the token, it sends a 
message to station 19, as directed by its interna! 
register NA and the cycle continues, in a circular 
fashion, from station 4 to 1 1 to 19 to 54 to 4 .. . 

Notice that the station numbers need not be contigu- 
ous. This relatively arbitrary station numbering (in the 
example) poses no inefficiency to the access method. 
The value of this is the ability to add and remove sta- 
tions (re-configure) on the network without re-arranging 
everyone elses addresses. (See section 3.2.2 for an 
example). 

In this way, the token is passed from one station to 
the next in a logical ring. 

3.2.1 ACCESS INITIALIZATION/ ERROR RECOVERY 

When the WD2840 is commanded into Network 
State, the Next Address Request (NAR) register and 
the NEWNA (CR10) flag must be used to define the 
Next Address (NA) register. When it is necessary to 
pass the token, it is passed to the current node 
number in register NA. If station NA is not on-line, 
determined by its lack of response, station NA + 1 is 
tried. This process continues until a station is found 



75 



which does respond. The responding station 
number is written into register NA so that this 

^ scanning procedure need not be repeated on sub- 

O sequent access cycles. 

00 NOTE: 1. Node numbers and 255 are reserved and 
^ cannot be used. Consequently scanning 

occurs circularly in the range 1-254. 
2. During Scan mode token passing to each 

node is only tried once. 

Anytime a station cannot successfully pass a token 
within two attempts, register NA is updated to 
NA + 1, and a new "next" station is searched for. The 
result is the removal of non-responding station(s) 
from the access ring. An interrupt (INS) is generated 
indicating a network exception caused a change to 
NA. 

The above description covers network recovery from 
station failure and purposeful removal of stations 
during on-line network operation. Setting stations in 
the scan mode can also be accomplished by sending 
control frames (a Scan frame redefines NA = MA + 1) 
over the network. The control frame may be directed 
to a single station, or all stations simultaneously 
(using the broadcast address). It is this scanning for 
new stations that permits on line addition to the 
access ring. 

NOTE: 

The policy of the SCAN frame is redefined by the 
user software as required by the application. For 
example: in a process control environment where 
stations are not often added while the network is in 
use, this procedure would be initiated rarely if at all. 

3.2.2 REMOVING A STATION 

There are two ways a station can be removed from 
the access ring: non-response due to station failure 
and non-response due to host commanded transition 
to the Isolate State. Both are treated identically from 
a network point of view. 

Referring to Figure 3.1, assume that station 19 is 
removed from the network (either physically or 
logically). In this example, station 11 would detect a 
network fault when trying to pass the token to 19 
(time TA would expire since station 19 will not 
respond). Station 11 detects this and finds the next 
station in the access ring by using the "scan" func- 
tion (similar to initialization). The next attempt at 
passing the token would be to station 20, register 
NA + 1. 

By starting the token ring recovery procedure at the 
intended station plus one (station 20) rather than 
MA + 1 (station 12) as is done in initialization, 
recovery delays are minimized (since fewer stations 
are tested for presence, 8 less in this example). 

The next station found would be number 54 in the 
example which station 11 writes into his register NA 
(now "patching out" dead station 19). The next time 
station 11 is finished with the token, it directly sends 
it to 54, making the sequence now 11 to 54 to 4 to 11 
to 54... 



3.2.3 ADDING STATIONS 

There are three primary methods by which a station 
can be added to a network. The first is a distributed 
method, in which each station in the network can poll 
for new stations in the gap between its address and the 
next address (between MA and NA). Second is a cen- 
tralized method, in which an individual station desig- 
nated by the network architect can interrogate the 
entire address space seeking a new station desiring 
INRING. The third — central scan — is a simpler (from 
the host point of view), centralized method in which a 
station can send a global frame causing all the on-line 
TACs to reset their next address register. This causes 
each TAC to poll its address space at its next token- 
pass attempt. Each method has advantages and 
disadvantages. 

Distributed Method 

The distributed method does not rely on a specific sta- 
tion. Thus, there are no problems or efforts spent 
selecting the administrator, nor is there any concern 
about backup administrators. In the distributive 
method, each station has the same responsibility to 
allow new access members as other stations. This 
method is the most host intensive and requires each 
station to maintain a timer (that can be configuration 
set as to its value) as to how often it should poll its gap 
for new stations. 

For example, assume the timer in each station is 5 sec. 
and that station 4's timer has expired (Fig. 3.2.3.1 ). The 
host attached to station 4 notes that the next address 
register (NA in the TAC) is set to 11, which indicates that 
a new station might be added to the network as station 
number 5, 6, 7, 8, 9, or 10. 

The host queues a frame into the TAC transmit chain, 
polling station 5. This frame will be sent by 4 with an 
acknowledgement requested from 5. If 5 is present it 
responds; otherwise, the TAC aborts its attempt after 
time TA. The TAC marks the result on the frame in the 
host memory space and proceeds with other tasks. 

After this exchange, the host, at its leisure, checks the 
transmit status of the frame. The host sees that the 
frame acknowledgement timed out, meaning that sta- 
tion 5 has not been added to the network, or that station 
5 is on the network and whether the request INRING is 
set in the network code field. In either case, the host 
takes appropriate action. If the desired INRING bit is 
set, station 4 changes its NA register to 5, allowing its 
next token to be passed to 5. This action puts station 5 
in the ring. 

Depending on an application's sophistication, a control 
message can be sent to station 5. That message says, 
"Your successor is X." In this case, X = 11, so that 5 is 
not forced to poll for its successor. In any case, 4 
updates its next address register to 5 and does not 
need to go through this distributive polling cycle again 
because there is no gap between 5's address and the 
next address; there is no possibility that a new station 
can be inserted between addresses 4 and 5. If 5 didn't 
respond to 4's poll, station 4 updates its poll counter so 
that the next time that the poll timer times out, station 6 
will be tried. 



76 



Host 
"Poll timer" 
'Poll counter' 




Host 




Host 




Host 










ii 




A 






MA = 4 
NA = 11 




MA = 11 
NA = 19 




MA = 19 
NA = 54 




MA = 54 
NA = 4 


1 


Adds 
5? 6? 
9?1 

i 


tat 
7? 
0?E 


on 
8? 
? 


< 


Add station 
12? 13? . . . 18? 

12? 
i ii 




ii 



Fig. 3.2.3.1 Distributed polling. Each host polls the 
gap in its address space for the possible addition of new 
stations. The host internal poll timer and poll counter set 
the polling rate and range as desired. 

If node 6 responds, its desired INRING bit is tested as 
above. If 6 does not respond, the host will queue a poll 
to station 7 the next time its poll timer expires. This con- 
tinues until the host completes 10, when the cycle goes 
back to 5 and repeats. In this example, with a gap of 6 
stations (between 4 and 11), and with a 5-sec. clock, a 
new node can be added within 30 sec. 

In the centralized station-addition method, a single sta- 
tion can poll the entire address space, seeking a new 
station that desires INRING. One reason for centraliz- 
ing this function might be the more careful control that 
can be placed in a network. There can also be optimiza- 
tions. For example, the central polling station can keep 
track of the stations that already exist and, therefore, 
bypass some address ranges. A polling station may 
know the network will never have more than, say, 75 
stations, In the example of Fig. 3.2.3.2, when station 4 
starts polling, it polls only to address 75 before reset- 
ting to zero. This works like the distributed method 
except that a single station does all the work. 




Fig. 3.2.3.2 Central polling. A single station — in this 
case, station 4 — dubbed "the administrator, " can be 
charged with all polling tasks. This simplifies the soft- 
ware in the other stations and centralizes network 
control. 



When the polling station determines that a station has 
been added, it must place the new station in the access 
ring. For example, station 4 is the centralized station 
doing all the polling (Fig. 3.2.3.2), and it discovers that 
station 27 has recently been added. Station 4 knows 
this because station 27 now responds to a first-time 
poll, and because its status bit is set, indicating that it 
wants to be added to the ring. (Some stations may be 
receive only, never desiring the right to initiate trans- 
missions.) Station 4 sends a high-level message to the 
software in station 19, telling it to change its next 
address register to 27. This message can also prompt 
station 19 to tell 27 its next address register should be 
54. This gets confusing, but it is all done with high-level 
software. These tasks are not real time and are quite 
efficient from the network point of view. 

Station 4, the administrator, need not create and main- 
tain a table of active stations on the network because 
the poll response returns three pieces of information. 
As node 4 polls the stations on the network, it finds out 
(a) that the polled station does not respond at all, as it 
would if it polled station 12 in Fig. 3.2.3.2 (b) that the sta- 
tion is already part of the network an is already in the 
ring or is receive only, as it would if station 4 happened 
to poll station 11 or 19; and (c) whether the station is 
attached to the network, is alive and wants to be in 
the ring, as is the case with a poll to 27. These indica- 
tions are conveyed by a combination of status bits sent 
back by the acknowledge frame. This acknowledge 
frame and status information are transferred at a TAC 
device level, so a host is not concerned with whether its 
station wants to be in the ring. The host simply sets up 
the proper bits in the control registers; the bits are 
relayed automatically by the TAC. Thus, with a simple 
algorithm, an administrative station can poll the entire 
network address range and know the network's exact 
membership and status. 

Central Scan 

Central scan is the simplest method of adding stations 
to a network. It involves sending a global frame to all 



































Host 






i 
1 




















MA = 4 
NA = 5 




MA = 11 
NA= 12 




MA = 19 
NA =20 




MA = 54 
NA = 56 












i 


k 






i 


i 






i 


k 


















"Set N 


"LI- 






^_to MA + 



































FIG. 3.2.3.3 Central scan request. A special com- 
mand can be sent by any station causing all attached 
TACs to set their NA register to the address of the next 
possible node. This causes each TAC to poll without the 
help of the host. 



O 
00 



77 



a 
to 

00 

o 



stations on the network, which forces each to update its 
own next address register to its station address plus 
one (NA = MA + 1). Assume station 4 is the central- 
ized station and sends the scan command frame (Fig. 
3.2.3.3). Station 11, upon receiving it, automatically 
sets its next address register to 12 (the TAC does this; 
the host is not involved but is notified of the situation). 
Also, station 19 sets its next address register to 20, and 
station 54 sets its NA register to 55. 

The result of this is a round of polling at the TAC level. 
Station 11, on completing its use of the token, tries to 
send it to 12. The token to station 12 times out because 
12 is not present. Station 11 reclaims the token trying to 
send it to 13 and so on, causing 11 to poll for station 
addition. The drawback of this is the huge time disrup- 
tion incurred by the simultaneous polling. 

It is not required that station 4 send this scan control 
frame to all stations at the same time. If it is known that 
station 11 exists in the network and that a station may 
be trying to add into the network after station 11 in the 
address space, a command can be sent to 11 telling it to 
set its next address register to 11 +1. Now 11 will go 
through scanning station 12, 13, 14 . . . again without 
intervention from station 11 's host software. This 
directed scanning has the effect of smoothing the poll- 
ing disturbance over a greater time. 

FIELD DESCRIPTIONS AND ENCODING 



The trade-off of all these methods is the software com- 
plexity distribution. If a TAC user assumes more 
responsibility, providing more intelligence distributed 
in the software, the system can be more sophisticated 
in handling new stations. If a user wants the TAC to han- 
dle this task itself, saving host software development, 
he pays only slightly in inefficiency. TAC gives the user 
an option. 

3.2.4 INTERACTION OF THE SUB-PROTOCOLS 

After a station is given the token, it will send an in- 
formation frame, a token frame, or a combination of 
both. It is this combination frame, referred to as a 
"piggy back" token, that causes the sub-protocols to 
interact slightly. 

In the normal case (no time-out), the SOURCE may 
transmit a combination frame to the DATASINK when 
his access period is over. All stations on the network 
observe this; after the reception of the current frame 
is complete, the one whose MA register matches the 
token address in the frame (TC) knows it has the 
token. 

In the case of a combination frame, the SENDer 
resets his timer TA on transmission complete and 
waits for the NA station to transmit something valid, 



TC 


The token control byte has the dual purpose of transferring access control between 
stations and conveying a request for immediate acknowledgement of the frame by its 
intended receiver. 




There is no interaction between the TC field and the DA or SA fields. Thus the token 
may be transferred to one station and data sent to the same or a different station, with 
one single frame. The value entered into the TC field is determined by the WD2840 
and does not appear in the buffer (except for transparent frames). 




TC Value 


Meaning 





Token not affected at this time. 




1-254 
255 


After current frame, the token belongs to station TC. 
(The sending station has recovery responsibility). 
Immediate ACK requested. Token not affected. 


NOTE: 

The sharing of this field prevents the passing of the token with data (piggy-back) and 
acknowledgement requests on the same frame. This combination is specifically 
disallowed because of its undesirable characteristics in network error situations. 


DA 


Destination address. Value of zero is reserved, 1 to 254 indicates the destination 
address of the frame. The value 255 is the global (or broadcast) address. 


SA 


Source address. The values of and 255 are reserved. A value of 1 thru 254 is the 
address of the sender of the frame. 


I 


Information Field. User defines format and content. 


FCS 


Frame Check Sequence. The FCS calculation includes all data between the opening 
flag and the first bit of the FCS, except for O's inserted for transparency. The sixteen 
bit FCS is compatible with the standard HDLC FCS. 


AC 


Access Control. Conveys supervisory information. May be sent as a command using 
transparent mode or received in response to an ACK/NAK request. Its format is 
shown below: 



78 



ACCESS CONTROL FIELD 



BIT# 


7 


6 


5 


4 


3 


2 1 


Name 


SCANF 


WIRING 











NVAL2 — NVAL1 — NVALO 



o 

IO 
00 



BIT 


NAME 


DESCRIPTION 


7 


SCANF 


Scan Mode (Command). Indicates that the addressed node(s) must redefine NA = 
MA + 1 for use on its next token pass. 


6 


WIRING 


Wants in ring (Response). This bit when set informs the node requesting the ACK 
frame that this node is not in the logical ring, but is requesting entry. It is the logical 
function of the transmitting node's GIRING .AND. INRING. (see CR1 3 and SR20) The 
WD2840 does not act on this information but merely passes it to the host via the 
ACK'ed frame's FSB. 


5-3 


— 


Reserved. 


2-0 


NVAL 


An encoded NAK/ACK value (Response). The receiving node will set one of the 
following codes depending upon the state of the last received frame: 

— No error 

1 — Insufficient buffers for frame 

1 — Receiver not enabled at frame start 

11 — Receiver overrun 

1 — Frame exceeded 16 receive buffers 



to verify his reception of the piggy back token. If the 
timer expires, the sender sends an explicit token (the 
data from the combination frame is assumed to have 
been accepted) and enters the normal token sub- 
protocol. 

The user is prevented from sending a combination 
frame and requesting an acknowledgement at the 
same time to prevent possible network state conflict 
under time-out conditions. 



3.3 FRAME FORMAT 

The frame format the WD2840 uses to transmit all 
data and control frames is similar to the industry 
standard HDLC. A 16 bit CRC is implemented and 
standard zero insertion (CRC16-CCITT) is used for 
framing. This framing method allows the use of 
standard network monitoring and diagnostic 
equipment such as data scopes and logic analyzers. 

Additional address fields and control points are 
defined as required to support the protocol. 



Normal Frame Format: 

F-TC-DA-SA-I-FCS-F 

F = Flag, binary pattern 011 11 110 

TC = Token Control (8 bit) 

DA = Destination Address (8 bit) 

SA = Source Address (8 bit) 

I = Information Field (0 to 4095 bytes or 16 

buffers, whichever is less). 
FCS = Frame Check Sequence (16 bit) 

Access Control Format: 

F- DA- AC- FCS- F 

F = Flag, binary pattern 01111110 
DA = Destination Address (8 bit) 
AC = Access Control Field (8 bit) 
FCS = Frame Check Sequence (16 bit) 

Token Pass Format: 

F-TC-FCS-F 

F = Flag, binary pattern 01111110 

TC = Token Control (8 bit) 

FCS = Frame Check Sequence (16 bit) 



79 



o 
10 

00 

o 



3.4 SENDING A TRANSPARENT OR 
ACCESS FRAME 

Two types of frames are transmitted under the trans- 
parent mode under user control. A scan access frame 
or a transparent frame. The format of the frames are 
described under 3.3 Frame Format with the transpar- 
ent format the same as Normal Frame Format. 

ACCESS FRAME COMMANDS 

There is only one Access Frame type permitted under 
user control — Scan Frame. The node that is 
addressed must redefine NA = MA + 1 for use on its 
next token pass. The format for sending this frame is: 



LINK(H) 


Pointer to next frame. 


LINK(L) 




00 (FSB) 




20h (FCB) 


Transparent frame, no 




acknowledge allowed. 


00 LENGTH (H) 


Access Control frame 




size (H, L). 


08 LENGTH (L) 




DA 


Destination Address or 




255 broadcast. 


80h 


Set Scan Mode. 



The FCB can be set for last frame, the acknowledge bit 
has no effect and no acknowledgements will be given 
to access frames nor will they be expected by the trans- 
mitting WD2840. 

The node receiving the access frame will only recog- 
nize a scan access frame as a command. Event count 
#0 will increment and the receiving node will set its NA 
to MA + 1 . Any other access code will increment Event 
Counter #7. 



TRANSPARENT FRAME 

Link(H) 
Link(L) 
FSB 

20H FCB 
XX Length (H) 
>08H Length (L) 
TC 



DA 
SA 
DATA 



pass token, broadcast, 
ackreq. 



The Transparent Data Frame allows a user to control 
the token pass, or TC field of a frame by using the first 
byte after length rather than the FCB. The frame trans- 
mitted will look like the User Info part of the buffer with- 
out the WD2840 firmware generating anything else but 
the flags and FCS. 

4.0 ELECTRICAL SPECIFICATIONS 

ABSOLUTE MAXIMUM RATINGS: 

Voltages referenced to Vss 

High Supply Voltage (Vdd) - 0.3 to 15V 

Voltage at any Pin - .03 to 15V 

Storage Temperature Range -55°C to + 125°C 

Electro-static voltage at any pin 400V (Note 6) 

NOTE: 

Absolute maximum ratings indicate limits beyond 
which permanent damage may occur. Continuous 
operation at these limits is not intended and should 
be limited to those conditions specified under DC 
Electrical Characteristics. 



OPERATING CHARACTERISTICS (DC): 

Operating Temperature Range 0°Cto +70°C 



SYMBOL 


PARAMETER 


MIN. 


TYP. 


MAX. 


UNIT 


CONDITIONS 


'DD 


Vdd Supply Current 




18 


30 


mA 




ice 


Vcc Supply Current 




160 


220 


mA 




vdd 


High Voltage Supply 


11.4 


12 


12.6 


V 




vec 


Low Voltage Supply 


4.75 


5 


5.25 


V 




V|H 


Input High Voltage 


2.4 






V 




V|L 


Input Low Voltage 






0.8 


V 




VOH 


Output High Voltage 


2.8 






V 


lO = -0.1mA 


vol 


Output Low Voltage 






0.4 


V 


lO = 1.6mA 


lOZH 


Three-State Leakage 






50 


M A 


V|N = VCC 


lOZL 


Three-State Leakage 






50 


ma 


V|N = 0.4V 


llH 


Input Current 






10 


ma 


V|N = VCC 


IlL 


Input Current 






10 


ma 


V|N = 0.4V 



80 



5.0 TIMING CHARACTERISTICS (AC): 



SYMBOL 


PARAMETER 


MIN. 


TYP. 


MAX. 


UNIT 


CONDITIONS 


CLK 


Clock Frequency 


0.5 




2.05 


MHz 


Note 1, 7 


RC 


Receive Clock Range 









MHz 


Note 4, 7 


TC 


Transmit Clock Range 









MHz 


Note 4, 7 


MR 


Master Reset Pulse Width 


10 






mS 




tar 


Input Address Valid to RE 









nS 




Trd 


Read Strobe (or DACK 
Read) to Data Valid 


2 




375 


nS 


Note 5, 2 


thd 


Data Hold Time From 
Read to Strobe 


20 




100 


nS 




tha 


Address Hold Time 
From Read Strobe 









nS 




taw 


Input Address Valid 

to Trailing Edge of WE 


100 






nS 




TWW 


Minimum WE Pulse Width 


200 






nS 




tdw 


Data Valid to Trailing 
Edge of WE or Trailing 
Edge of DACK for DMA 
Write 


100 






nS 


Note 2, 3 


twrr 


CS High Between 
Writes 


300 






nS 




trdr 


CS High Between RE 


300 






nS 




Trr 


RE Pulse Width 


375 






nS 




tdak 


DACK Pulse Width 


375 










tahw 


Address Hold Time 
After WE 


80 






nS 




tdhw 


Data Hold Time After WE 
or After DACK for DMA 


100 










TDA1 


Write 






80 


nS 




Time From DRQO (or 




DRQI) to Output 














Address Valid if 














ADRV = 1 












tdao 


Time From DACK to 
Output Address Valid if 
ADRV = 






375 


nS 


Note 5 


tdd 


Time From Leading Edge 
of DACK to Trailing 
Edge of DRQO 
(or DRQI) 






375 


nS 


Note 5 


tdah 


Output Address Hold 
Time From DACK 


20 




100 


nS 




tdmw 


Data Hold Time From 
DACK For DMA Read 


20 




100 


nS 


Note 2 


ttdv 


TD Valid 


100 






nS 




TSRD 


RD Setup 









nS 




thrd 


RD Hold 


320 






nS 





a 

00 

o 



NOTES: 

1. Clock must have 50% duty cycle. 

2. There must not be a CPU read or write (CS-RE or CS-W E) within 500 nanoseconds after the trailing (rising) edge of DACK. 

3. There must not be the leading (falling) edge of DACK allowed within 500 nanoseconds after the completion of a CPU write (CS-WE). 

4. See "Ordering Information" for maximum serial rates. 

5. C(load) = 100pf 

6. Measured by discharging a 100pf capacitor to each pin through a 1 K ohm resistor. 

7. TC/RC must be <43% of CLK when transmitting multiple buffers. 



81 



iZcmsV; 



— ^ 

[*- T AR*- 

'I 



- T RR- 



-= A Tha k- 

y DATA \_ 
A VAL'D / 



Y* T RD 



/ DATA \ 

N WLID / 

i *\*\ Thd \* — 



IA0-IA3 



DAL0-DAL7 



X 



X 



X 



- T AW- 
- T WW- 



- T DW- 



3TT 



T AHW 



< 



DATA VALID 



> 



—*i t dhw r+— 



CPU READ (CS IS LOW) 



CPU WRITE (CS IS LOW) 



DRQO. 



-*| TDD fc 



A0-A15. 



(ADRV = 0) 



< 



A0-A15 
(ADRV = 1) 



-*H T DA1 [♦ +j [<-TdA0 

Tdak-^I t dah 



> 



DACK 
DAL0-DAL7 



X 



^ 



L, 



-<^ DATA VALID N 



K 



T RD- 



DRQI- 



(A0-A15 SAME AS DMA OUT) 
|«*- T DD-*-| 



s 



DACK- 



DAL0-DAL7 



- T DAK ■ 



X 



I T D w |1"dHW 

] ■ * Vk 



< 



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DMA OUT 
6.0 ORDERING INFORMATION 



DEVICE NUMBER 


MAXIMUM RATE 


WD2840-01 
WD2840-05 
WD2840-1 1 


100 Kbps 
500 Kbps 
1.0 Mbps 



Package Diagram 



,0 ° ,„„ - 610 

MAX , 2430 ° 15 , MAX , 

* k MAX H min [■« V| 


Tumi 

.035 X \^_ 

.055 n I 

,014_ to _ 
.021 


fMfflmwtxxi 

^ 1 1 MIN 



DMA IN 



nM k— t dv 



T SRD»| " | " | « T HRD 



TD-RD TIMING 



82 



WD2840 



RFTtmU TO 
ISOLATE, 
GENERATE 
MODE CHNG 
INTERRUPT 



BEGIN! SEQUENTIAL 
SCAM TOR SUCCESSOR 




i 


| UK*- 


— MA+l 1 


L 


OLE 


) 



RDM\D='5 



rcadr-«-last(h,l) 
input next(»,l) 



NXTT0«-0 




FOUND HERO - 

LINK VALUE SET 

LAST FRAME FLA6 

TO CAUSE TOKEN 

BASS AT CURRENT— 

FRAME END. LA5TF-*-! 



LAST*- NEXT 
BFRCMT* — 
BFffCUT -|- 1 



"TSITUf^ 
YES 



WHILE! TX DMA 13 RUNNING, 
GET THE CURRENT BUFFER S 
LINK HELD USING, DAE RCDMA. 



UPDATE ADDRESS OF 
LAST TRANSMIT BUFFER 
AMD INCREMENT BUFFER 
COUNT 



TKANSMISSOM 
ERROR EVENT 
COUNTER 




^TUR = 1 
TRANSMITTER \. ? 
UNDERUN? ^ - 
"TSTEOF", 
FRAME STILL 
IN PROiffESS ?^<1„ . >0/ES 



AO0JAK RESPONSE 
£XP£CTEZ> T 
YES 



WHTE'NORMAL' 
FSS WTO 
'TOME HEADER 



I DROP RTS 



( IDLE 3 ) (FRMEA/D 



SELECT FSB WLLIE 
"TRANSMITTER 

UNDERUN" 



WRITE F5BV/MJE 

INTO 
FRAME HE4PER 



IHPUT AMD 
DISCARD TWO 
LINK BYTES 

1 




(frmend) 



SEI£CT FSB VALUE 
'TOO MANY BUFFER" 




T5EWT*-0 
NXTTO'*- 1 



UGLY ERROR; TYCWAIN 
IUTE&RITY IN QUESTION. 
FORCE EXPLICIT TOKEN 
PASS AND BURST END. 
DONOTADVANLECHAIN 
BEYOND TUST POSTED 
FRAME. 



TOKEM ALREADY PASSED 
PI66YBACK OM DATA FRAME? 



$ 



( IDLE 3 ) 



( IDLE g ) 



TRANSMITTER F10W 



TKIGCER 

TTERR 
IMTERRUPT 



C FRIVOID 



/ 



Z&AO REVI5I0KI4.O TOMIL>5 MARCH i'&l 



WD2840 



WD2840 



(TRANSMIT ^ 

T 



YES ARE DATA FRAME. 
TRANSMISSIONS 

PERMITTED 
NO 




LAST**— 

TXCH/AIM 

BASE 



« "GETKDYTDTX" 



NXTT0-«-1 
LASTF-»-0 



PREPARE TO 
TRANSMIT 
NEXT FRAME 



FRMn"-*-FRMCT + 1 
SFRCT-— 



TXMAR'--TXEHA/W 
TXUA4--BS/Z 




SHOW cum 

FRAME IS L/IST ImsTF-"- J 



NOTE P16&Y&ACK 
"TOKEN, ALSO END 
CURRENT BUESTT 



ZMD REV/SIDN40 RDMID--S MATCH V&3> 



(RECEIVE!? ) 

| KEEP TC OR DA BYTE 



GET FIRST BYTE 
HANDSHAKE 
RCVR -U.C 



FRAME END 
AflDT TOST 
BYTT? 




TOKEN JUST 
PREVIOUSLY PASSED ? 



TOKEN PASSED OKAY, 
TOKEW RESPONSIBILITY 
WOW £A/DED,/NDICATF 
NODE IS " IN- H INC 



IF ?WD BYTE MOT 
READY, G£T RECEIVE 
BUFFER ADDRESS 
'(IFWOTDOWE) 



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RECEIVED 
TOKEN PASS 
1ST BYTE 
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ACCESS CNTRL FRAME RC 
ERROR EVENTCDUNTER 



MDFKM0" 



'Glff/MS = 1 
? 

,'Y£S 
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WAIT FDR 
FRAME END 
OK 2ND BYTE 



IF 3RD BYTE NOT 
KEADYGETirEDVE 

JUFRADOR . 

QFJOTDOWE) 




("TRANSMIT ) 




RECEIVED ACCESS 
CONTROL FRAME 
JST BYTE : DA 
2ND BYTE : AC 

BAD 



© 



SCAN MODE 

FRAME KC'ED 

EVEWT COUNTER 



INCREMENT 
EVENT COUNT 



BUFFER STRUCTURE 



y 



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BYTX 



V 




1 

2 


V 


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\ 


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4 T 



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RCEKTOR EVENT 
COOWTER 



( 'OLE ) 



CALCULATE" 
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AC BYTE 



wa/tfdr 
.frame end or 

3RD BYTE 



network frame structure: i 

data: f-tc-da-sa-i-fcs-f 
access cntl: f-da-ac-fcs-f 
token: F-TC-FCS-F 




(F17MEK1D) 
(TRANSMIT) 



RECEIVER FLOW 



2&A0 REVISION 4.0 ROM ID- 5 MARCH 3,'<S3 



WD2840 



WD2840 



(SCIUD ACK MAK FRM) 

. I . 

SbACK-<-0 




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wo rin6"ifd£5ired 

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7 




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LIWK FIELD 

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WXTR(H,L) 
*-DMA(H,U 



UPDATE NEXTKECEIVE 
SUITER ADDRESS REb 
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WXTR2S' ■ 



CMZD 



CsaiD TDKEAP) 

\ 'sen dtoken" 



mm if re 

PROVIDED W/KZ. 




PESPONDTD ACK REQUEST 

OWIYIFFWIMEALWED 

TD THIS NODE - 




( RET ) 



(TX WRITE" FSB) 



-A£l| 



7XMMM/IR*- 



save res 

VALUE 



CALCULATE 
FSB ADDRESS 
IN HBtDER 



USIMiTX DMA, WRITE 
FSB INTO FRAME HEADER 



( *CT ) 



( *^ ) 



^&40 REVISION 4.0 K0M1D=5 MARCH "^,'£.3 



CR) EXPECTIMCa 
V ArkVMAK I 



ACK/NJAK FRAME? 



"T5TWT4ACK" 



SETUP RCVR DMA 
MAR"*-NE)(T+£ 
ENABLE RC DMA 



LAST*-N£XT(Hi-> 




SET MAK CODE 

TO 
"OUT OF BUFFERS' 



(IblE 3 ) 



(jXWhMk/mrwm 



SHUT DOWN 
KOIR DMA 




CALCULATE FRAME 
L£N6TH,WRnEINTO 
HEADER VIA TX DMA 



TXDMA*-tAST 



DMA(H.L>*-FRAME 
FSB ADDRESS 



READ LAST BFRS 
LINK FIELD-**/ XTR 



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irdr interrupt 

EVENT 



SET NAK CODE TO 
"RCVR 0VEKUN' 



DUPLICATE' STATION 
ADDRESS DETHTED v r 



| SPACE-- <Z> 



INCREMENT 

EVENTCOUNHK 

# A 




s 



=® 



CETED 



SET AOC CODE 
"NO EffROK" 

I 



SEND ACK 
FRAME TO TOKEN 
HOLDER 



( StobAtK'/NMnWlt: 



2&40 REVISION 4.0 ROMID-5 MARQJ */S3> 



WD2840 



WESTERN DIGITAL 

CORPORATION 

WD2840 Application Note 



INTERFACING THE WD2840 TO A VERSABUS 
SYSTEM USING A DUAL PORT MEMORY 

This application note describes one possible method 
of interfacing the WD2840 Token Access Controller 
with a general purpose microprocessor based sys- 
tem. This is intended to be an example design only, 
no effort has been made to minimize the logic re- 
quired to perform these functions as would be done 
in a production design. Rather, the design has been 
kept "clean" to promote readability. 

This implementation is designed with a dual-port 
memory concept allowing its use in systems that 
either do not support DMA at all, as well as systems 
that are unable to guarantee reasonable DMA re- 
sponse to a request (Figure 1). Examples of these 
systems are low end personal computers that allow 
their disk controllers to "hog" the DMA channel for 
an entire sector transfer. Very high end systems are 
also candidates for the dual-port memory technique. 
Here, the system bus may be shared by multiple 
hosts and be of such extreme bandwidth that the 
internal WD2840 DMA controller may be inefficient. 

In most applications, the WD2840, can simply self- 
DMA its data directly to/from the host system's work- 
ing memory. In the applications described above, the 
WD2840 must DMA its messages to/from the net- 
work into a local RAM allowing the host to access it 
at its leisure. 



REFERENCES 

WD2840 Token Access Controller Specification, 
Western Digital Corporation, 1983. 

"Token Passing Cashes in with Controller Chip" 
Electronic Design, October 14, 1982. 

Versabus Technical Reference Manual Motorola, 

RS-422 Technical Specification 

This design is described in six sections: 

Host dependent logic, here designed for the 
Motorola Versabus system, including all required 
bus interface drivers and timing. 

Local two-port buffer memory which is shared by 
the host and the WD2840. 

Arbitration logic to fairly share the buffer memory, 
especially when both the host and WD2840 de- 
mand access at the same time. 

WD2840 Token Access Controller and associated 
timing 

Media interface consisting of a manchester 
encoder/decoder and liner drivers 

Generalized initialization flowchart 



C 



r' 



DRIVERS/ 
RECEIVERS 



Tt" 



HOST 
INT 



CONTROL 



TAC / HOST ARBIT 
TIMING 



ADDR 
DECODE 



=£ 



ADDRESS/16 



m 



BASE ADDRESS: FF4000 
INTERRUPT LEVEL: 6 
INTERRUPT VECTOR: #255 



2840 

AND 

CONTROL 



JI 



MAN- 
CHESTER 
ENCODE 
DECODE 



MEDIA 
INTERFACE 



Figure 1 . Versabus Application of WD2840 Using Dual Port Memory 



89 



to 

c 

CD 

ro 



DATA DRIVER ENABLES 
NENEN 





1 

1 
1 1 



REC FM. HOST 

ILLEGAL 

OFF 

DRIVE HOST 



Dl 




*-• 



D8" 



m 



DIP 



DT3 



DT3 

33E 



A10 
1 13 



242 
A9 



DS1 



RESET 



WRITE 8 



ACKIN 11 



SYSRESET 13 



ACKOUT 15 



240 
A8 



s» 



DO 



D1 



TACS 1 



D7 



T7 



C9 




1119 



D9 



D10 



;l 



te* 



IROQ 



IRQ6 



D12 



D13 



D14 



D15 



ADDR SET UP DLY 



+ 5 _4 
DSA1 5 



DSA2 



16 


2 1 


14 


RESET *■ 


12 


HWRITE 


9 


ACKIN 


7 


RESET 


5 


3 


HWRITE 



7g> 



12 
FC9 



3DSA 



B3 
175 



2 DSA1 



1X_T19 



DATA/CONTROL 



A01 


2 


A02 


4 


ATJ3 


6 


A04 


8 


ATJ5 


11 


A06 


13 


A07 


15 


A08 


17 



l> 

A7 
240 



YZ 



18 A0 



16 A1 



12 A3 



£09 


2 


A10 


4 


AIT 


6 


ST? 


8 


A13 


11 


A14 


13 


ATS 


15 


AT6 


17 



> 



TACS>- 



13 



19 



A19 






13 



A6 



A8 



A9 
A10 

ALL 
A12 
A13 
A14 
A15 



A5 
LS240 



>> 



T^J 



18 

16 

14 

12 

9 

7 

5 

3 

19 



DSA3 4 



AMMEMAD 



B4 V 



GND 



+ 12 



3,4,23,24,27,28,31,32 
61,62, 119, 120, 135-140 



1,2, 129, 130, 131, 132 



121, 122 



ADDRESS MODIFIER 



AMO 



^> 




A13 



6 AMIACK 



7AMMEMAD 



8 DEVSEL 



LS30 



HOST INTERFACE 

The host interface (Figure 2) utilizes common three- 
state bus drivers buffering the Versabus from the 
internal data bus. They are enabled low-Z onto the 
host bus whenever the host "reads" from the local 
memory (or WD2840 registers) and are enabled to 
drive the internal bus whenever the host writes to the 
internal memory (or registers). All other times these 
are hi-Z allowing other modules on the Versabus side 
to use that bus, as well as allowing the WD2840 to 
use the internal bus. Only an eight bit internal data 
bus is used mapping all host memory accesses into 
the lower byte. (Bus drivers A10 and A1 1 are not used) 

Sixteen address bits are buffered and driven onto the 
internal address bus when the host has access to the 
RAMs (otherwise the WD2840 drives the internal ad- 
dress bus). The additional address lines of the Versa- 
bus are "anded" with the I/O Data Strobe signals DSO 
and DS1 and address modifier bits creating a device 
select signal (DEVSEL) when all are active simultan- 
eously indicating the host actually wants to access 
this module. 

The Host Interrupt and Driver control logic (Figure 3) 
supplies the host interrupt vector (OFFH) when 
acknowledged (C10). Acknowledgement occurs 
when the Versabus ACKIN is received in conjunction 
with the proper priority level (set at 4 in this design), 
the proper address modifier (AMIACK), a short de- 
skew delay (DSA3), and a signal indicating an 



interrupt was indeed generated by this module 
(IROQ). 

The logic on this sheet also controls the direction of 
the data buffers previously described (with signals 
EN and NEN), presuming the host has active control 
of the local bus (HOST = 1). The host requests con- 
trol of the bus for access to the on-board RAM and 
during interrupt acknowledgement. 

CLOCK/ARBITRATION 

This logic (Figure 4) generates the synchronous 
timing used in the rest of the sections. A 16MHz 
signal derived from a crystal oscillator (part of the 
manchester logic, described later) is buffered (by C9 
and then called FC). This high speed clock is also 
divided down for the WD2840 system clock CLK at 2 
MHz (other slower rates are not used in this design). 

This high speed clock clocks a simple latch (B7) until 
either the host or the WD2840 request local bus 
access. If the host desires access to this module, 
HOST is made true, the on-board WD2840 DMA re- 
quest generated TACDRQ. When either (or both) of 
these signals occur, IDLE goes false (B5 pin4) 
freezing the state of latch B7. 

IDLE going false starts the timing chain (B1, C1) that 
generates general timing pulses used later. 

When the local memory sequence is complete, at 
time T10 for the TAC (B8 pin 6) or at time T7 for the 




i©- 



3 ACKOUT 



VALID ACK 4 



DEVSEL 



ceTV 



6 HOST 15 



LS08 



fe 



5 HOST 



LS240 



HWRITE 9 



REG 1 



zj°E> 







2 


240 

-£>• 

C10 


18 DO 






4 


16 D1 




6 


14 D2 






8 


12 D3 




11 


9 D4 




13 


7 D5 




15 


5 D6 






17 


3 D7 










VALIDACK 4 


N 




V ' 


19 


TACS 5) C4 






? 


INT 


VECT 


OR( = FF) 



HOST 



HWRITE 



(READ) 



E> 



3 HRAMON 



LS32 



3°0E)" 



8 EN 



10] Ol\ 



(DATA TO HOST) 



8 NEN 



(RCV FROM HOST) 



Figure 3. Host Interrupt and Driver Control 



91 



host (B2 pin 6) a special end of cycle delay is initiated 
(via shift register E7). This delay ensures that at least 
500ns is maintained between WD2840 DMAs and 
possible host I/O accesses. At the end of this delay, 
flip-flop B6 generates a one clock "DONE" pulse re- 
setting the arbitration logic. 

MEMORY ARRAY 

The memory (Figure 5) uses simple static memories 
configured as 8K by 8 bits. The RAM data lines are 
buffered onto the local data bus due to loading 
considerations. The RAM array is enabled during all 
I/O operations except those to the first sixteen 
locations, which are used for accessing the sixteen 
internal WD2840 registers (REG). 

WD2840 SUPPORT 

The WD2840 interface logic is given in Figure 6. The 
system clock (CLK) is derived from the timing 
generator (Figure 4). (This clock may be asyn- 
chronous with the transmit and receive data clocks if 
desired.) Address latches are used in this design to 
provide additional signal drive and to improve 
memory access timing (the WD2840 does have inter- 
nal address latches that are useful in less stringent 
applications). 

Host Write (HWRITE) is used to control the direction 
of I/O operations with the WD2840. When true, the 
WD2840 expects its internal registers to be written 
into. This occurs when both WE (pin 3) and CS (pin 4) 
are both low. Gate C7 1,2,3 ensures that the WE* 
signal goes false prior to the data changing (ensures 
hold time). Chip select logic (D10, 1,2,13,12) enables 
reads or writes only when the host has access to the 
internal bus, the internal address bus holds a value in 
the range of 0-15 (REG true), and a short set-up timer 
has expired (T1). 

Gate F10 (11,12,13) "ands" the WD2840S DMA input 
and output requests and presents them to the arbitra- 
tion logic described earlier (via TACDRQ). The sense 
of the WD2840 DMA request (input or output) is 
latched (with E10). The DMA output signal is delayed 
for RAM setup (T2) and turned off before the data is 
removed to meet RAM hold timing (T7) and presented 
to the RAM control logic to generate the write pulse. 



MANCHESTER ENCODER/ DECODER 

The manchester encoder/decoder used here is a 
Harris HD-6409 (Figure 7). This device is ideal for use 
with the WD2840 in that its "invalid manchester 
output," that detects missing clocks, etc., can be 
directly connected to the WD2840's SQ input. A 16 
Mhz crystal controls the internal digital phase locked 
loop used for clock recovery and generated the 16 
Mhz master clock (FC) used for general timing in this 
design. 

The "modem" consists of a simple RS-422 balanced 
driver and receiver. More elaborate media inter- 
faces are possible, including FSK and broadband, 
depending on speed / distance / number of taps / cost 
requirements. 

INITIALIZATION 

Figure 10 "flow chart" gives a generalized method of 
initializing a WD2840 based communications sub- 
system. First the WD2840 internal diagnostic are 
preferred, followed by loading of station parameters. 
Next the network is tested for activity and potential 
duplicate addresses. Finally the WD2840 TXEN is set 
allowing normal network generation. The Host now 
simply monitors TX and RX chains to sent/receive 
network data. 

SUMMARY 

This application note details a simple WD2840 sub- 
system designed around the VERSAbus form factor. 
The on-board RAM makes removes any DMA/host 
bus access questions from the system design. A very 
simple line driver allows a number of these modules 
to communicate at speeds of 1 Mbps. 

Note that this application note is intended for illustra- 
tion only; simpler and more elaborate interfaces are 
possible. 



92 



o 

o 
o 

0) 

3 
Q. 

> 



FROM 
MANCHESTER 




IDLE 3 



T1 



T2 



T3 8 



T4 13 



T5 14 



T6 17 



T7 18 



DO 273 QO 
B1 Q1 
Q2 



T5 



STATE GENERATOR 



2 I B8 

LS08 




D O 

175 u 

D Q 

D Q 

D Q 



2 TACS 



3 TACS 



r05> 



HOST 



LS02 



-NC 
C9 



4> 



7 IDLE 



LS240 HOSTS 



13 B8 



LS08 



11 HOSTGNT 



LS08 



T10 



_5l B8 

LS08 



D7 




!H 



T8 3 


273 
C1 


2 T9 


T9 4 


5 T10 


T10 7 


6 T11 


T11 8 


9 T12 


T12 13 


12 T13 


T13 14 


15 T14 


T14 17 


16T15 


T15 18 


19T16 


FC11 






f - £ . 





B2 
LS11 



LS02 



TAC/HOST ARBITRATION 



RESET 



R1 4 
LS240r 2 7 

R3 8 
R413 
R514 
R617 
R7 18 
FC11 



LS2 

4>A 



D 74 
B6 
> r 



273 
E7 



2 R1 

5 R2 

6 R3 
9 R4 
12 R5 

15 R6 

16 R7 
19 R8 



^t 



T8 



DRQIL 



TACW 



C3 
157 



S32 r S E L_!r— \ 



CO 

C 

3 



2 

(D 

3 

o 

> 



!|>!J 



F11 LS240 



TACGNT 



HOSTGNT 



13 / 



+ 5- 



r*l 



A 

B C8 
C 

138 



14 


RCS1 


13 


RCS2 


12 


RCS3 


11 


RCS4 


10 


RCS5 


9 


RCS6 


7 


RCS7 











RAN/IOE 



4118 
D1 



WE 
OE 

C5 

Vcc 
12* 241 



RCS1 



+ 5 



4118 
D2 



3 JbQo-!- 
J LS02 



RCS2 18. 



4118 
D4 



A8 



23 



RCS3 18, 



DO 


2 


244 
C12 

->- 


18 


RDTO 


D1 


4 


16 


RDT1 


D2 


6 


14 


RDT2 


D3 


8 


12 


RDT3 


D4 


11 


9 


RDT4 


D5 


13 


7 


RDT5 


D6 


15 


5 


RDT6 


D7 


17 


3 


RDT7 











!40 K_ 



u 



4118 
F1 



4118 
F2 



4118 
D5 



RCS4 18 



4118 
F4 



RDTO 



RDT2 



RDT3 



RDT4 



15 



RDT5 



4118 
F5 



RCS6 



RCS7 



RDTO 


2 








18 


DO 


RDT1 


4 


244 
C11 


16 


D1 


RDT2 


6 


14 


D2 


RDT3 


8 


12 


D3 


RDT4 


11 


9 


D4 


RDT5 


13 


7 


D5 


RDT6 


15 


5 


D6 


RDT7 


17 


3 


D7 














T 

— ( 


>— 


T9 




RAMOE' 







(Q 

C 

3 



D 
N> 
00 

■b 
o 

0) 

c 
■o 
■a 
o 



HWRITE 



C1M (1MHZ) 




HOSTGNT 3 



^y-^n 



TACS 




-i-ov 



5V 

G12 
16, 



BPBRESET 7 
FT^I 



LS08 



D9 



IA0 
IA1 
IA2 
IA3 

TD 

RD 

TC 

RC 

RTS 

CTS 

SQ 



RE (OUT OF 2840) 
WE (TO 2840) 
CS 



INTO 
DO NOT CONNECT 



48 

+ 5 



42 

+ 12 



T 



DO QO 
B12 
373 



OC 



B11 
373 



8 DO 



9 D1 



10 D2 



11 D3 



13 D5 



A10 



43 TACINTR 



A4 


1 




A5 


2 




A6 


13 


L2 


A7 


3 




A8 


4 




A9 


5 


r: 


A10 


9 




A11 


10 




A12 


11 


15 



B>h|™> 



8 REG 



X9 



3REG 



REG/RAM DECODE 



IDLE 9 



E10 
D QP 

D Q 



T 



T7 4 
3 DRQOL 5 



7 DRQIL 



DloV 



,6 TACW 



I 13 . 

12 FIOVLI 




NVM 

SD HD6409 

MANCHESTER 



ENCODER 
DECODER UDI 



CO 



Q 



J- R1 -L 

"p2 ci[ 



RTS12 




RS422 
RECEIVER 



16 MHZ OUT FC 

► 



i\ 



CX) 



v 



r 



1. C1, C2 = 32 pf 

2. R1 = 15 Mr, 1/4W 

3. Xi = 16 MHZ, AT CUT PARALLEL RESONANCE 
FUNDAMENTAL MODE 

4. RT = DEPENDENT ON FREQ & LENGTH APPROX. 90-2402 



Figure 7. Manchester Encoder/Driver 



96 



HOST TIMING 
—*>\ [*— 62.5 ns. 

Fc_JTJ-lJXriJlJTriJTJlJTJTJTJTJTJ^ 

„ .-.: i ■ " ' ! ' 'i 


i , ' ' ' ■ 


i • i , i t ( 


l 


DSA ' | 

1 1 1 


1 ' 


, '' /- 


1 1 


DSA3 ' 


1 1 


1 




1 1 1 


i 


DEVSEL . 


J 1 1 


i.i' > 


1 


1 1 1 

HOSTS ' 


1 1 


' I 


( | 






111 


1 


1 


1 | 


i.i \ 


1 | 


• ' ' 


' 1 1 


.i.i ' \ 


1 


T3 III 


I 1 


_r-r , - - t- \ 


1 


1 ' ' 


1 1 


1 1 ... , \ 




T5 "I" 


1 1 


' 1 '' ■• \ 


I 


1 ' 1 


1 1 


' ' ' r-r-. ' 


;' 


' ' » 


1 1 


.ii.i 


III 


1 


r i i i . 


TAnr.R i ' ' 


1 1 


. . IAU HL. L.AIA VALIU 

1 ' ■ i : y 


WE(TAC) 1 I 


1 I 1 " 


| 1 


1 ' ' > i , / 


1 ' 1 


1 1 


iii' ■ / 




HWRITE 1 | | 

RAM^F , „ 


| 1 


i , i ■ i i /fc^ 


1 1 

RAMT 


1 1 


i i 1 i > i / t 1 


RAMWE . | • | 


1 I 1 " 


1 1 


' "I" 1 '—" y* 


. i 


DTACK ' 


| 1 




1 


1 I 1 1 ' y 




ABTRST 


! ' 


►! WRITE WIDTH U 

1 770ns ' 


l r 



Figure 8. Host Timing 



97 



FC 
DRQO 






TACS ( TACGNT) f 

IDLE 

DRQOL 

T1 

T2 

ADDR STB 



* 



RAMWE 



RAMOE 



RAMCE 



DTACK 



I I 



I I I 
l I 



I I 



i — r 

l i 



1— h 



i i i 
i i i i 



i I ' 
-i — i — i — \- 



i i 



-\ — i- 



i i 



jtt 



Figure 9. TAC Timing 



98 



(master reset) 
T 



c 



CHECK REG 8-F 
WITH (55.AA) PATHENAL 



SEE DIAGNOSTIC 

STATE FLOW CHART 

IN WD2840 

DATA SHEET 



CHECK W/R 
REG 



DIAGNOSTIC 
TESTS 



SET A 

SOFTWARE TIMER 

T S <TD 



INITIALIZE 
1 'SYSTEM CONSTANTS 



TA - REG8 
TD -» REG9 



CO 
<p 

c 
■o 
c/> 

<D 



AHOLT - REGD 
TXLT - REGE 



MA - REGF 



NAR - REGC 

(MA +1) 

IF NA UNKNOWN 



CBPL -» REGB 
CBPH - REGA 



CHECK FOR 
¥ NETWORK DEAD 



CR1 — 00 
CRO - 00 




YES 




CR1 - 28 
(INIT, GIRING) 



NETWORK IS ACTIVE 



CHECK FOR 
DUPLICATE MA 



SET SOFTWARE 

TIMER T S 

< SCAN TIME 



TOKENS WILL 
BE PASSED BY 
SCAN METHOD 
IMPLIMENTED ON 
IETWORK 
(SCAN TIME) 




CRO - 50 
(TXEN) 



WAIT FOR 
ITOK INTERRUPT 




1ST ITOK GOES 

INTO SCAN, WHEN 

PASS SUCCESSFUL 

INRING = 1, 2ND 

ITOK INRING = 1 



IN NETWORK 
PASSING TOKENS 



IF PERMITTED 

TO INIT TD^ 

SOME UNIQUE 

VALUE 



OK TO ENTER 

ACTIVE 

NETWORK 



EO - CR1 
(E4 - CR1) 



ITOK INTERRUPTS 

OFF TO REDUCE 

PROCESSOR 

OVERHEAD 



IF ALLOWED 
TO INIT 



SET-UP WHEN 

ALLOWED TO 

TX & RX FRAMES 

(INIT ON) 



ISOLATE 

FROM NETWORK 

CRO - 01 



DUPLICATE 

ADDRESS 

TAKE RECOVERY 

ACTION 



WD2840 WILL AUTOMATICALLY 

FOLLOW TX&RX CHAINS 

AS THEY ARE ENABLED, 

MONITOR INTERRUPTS, 

(EVENT COUNTERS) 




Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital 
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by 
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change 
specifications at anytime without notice. 



WESTERN DIGITAL 



2445 McCABE WAY 
IRVINE, CALIFORNIA 92714 



(714) 863-0102, TWX 910-595-1139 



100 



Printed in USA 



WESTERN DIGITAL 

CORPORA T I O N 

2445 McCabe Way • Irvine, CA 92714 
(714) 863-0102 • TWX 910-595-1139